^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl_topology.h - Intel HDA Platform topology header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-15 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SKL_TOPOLOGY_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SKL_TOPOLOGY_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/hdaudio_ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <uapi/sound/skl-tplg-interface.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BITS_PER_BYTE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MAX_TS_GROUPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_DMIC_TS_GROUPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_FIXED_DMIC_PARAMS_SIZE 727
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Maximum number of coefficients up down mixer module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UP_DOWN_MIXER_MAX_COEFF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MODULE_MAX_IN_PINS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MODULE_MAX_OUT_PINS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SKL_MIC_CH_SUPPORT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SKL_MIC_MAX_CH_SUPPORT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SKL_MIC_SEL_SWITCH 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SKL_OUTPUT_PIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SKL_INPUT_PIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SKL_MAX_PATH_CONFIGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SKL_MAX_MODULES_IN_PIPE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SKL_MAX_MODULE_FORMATS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SKL_MAX_MODULE_RESOURCES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum skl_channel_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SKL_CHANNEL_LEFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SKL_CHANNEL_RIGHT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SKL_CHANNEL_CENTER = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SKL_CHANNEL_LEFT_SURROUND = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SKL_CHANNEL_CENTER_SURROUND = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SKL_CHANNEL_RIGHT_SURROUND = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SKL_CHANNEL_LFE = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SKL_CHANNEL_INVALID = 0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum skl_bitdepth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SKL_DEPTH_8BIT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SKL_DEPTH_16BIT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SKL_DEPTH_24BIT = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SKL_DEPTH_32BIT = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SKL_DEPTH_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum skl_s_freq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SKL_FS_8000 = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SKL_FS_11025 = 11025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SKL_FS_12000 = 12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SKL_FS_16000 = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SKL_FS_22050 = 22050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SKL_FS_24000 = 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SKL_FS_32000 = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SKL_FS_44100 = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SKL_FS_48000 = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SKL_FS_64000 = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SKL_FS_88200 = 88200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SKL_FS_96000 = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SKL_FS_128000 = 128000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SKL_FS_176400 = 176400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SKL_FS_192000 = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SKL_FS_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum skl_widget_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SKL_WIDGET_VMIXER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SKL_WIDGET_MIXER = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SKL_WIDGET_PGA = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SKL_WIDGET_MUX = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct skl_audio_data_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum skl_s_freq s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum skl_bitdepth bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 channel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum skl_ch_cfg ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum skl_interleaving interleaving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 number_of_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct skl_base_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 cpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 is_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct skl_audio_data_format audio_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct skl_cpr_gtw_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 dma_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 config_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* not mandatory; required only for DMIC/I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 config_data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct skl_dma_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 config_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 config_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct skl_cpr_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct skl_base_cfg base_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct skl_audio_data_format out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 cpr_feature_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct skl_cpr_gtw_cfg gtw_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct skl_cpr_pin_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 sink_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct skl_audio_data_format src_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct skl_audio_data_format dst_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct skl_src_module_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct skl_base_cfg base_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum skl_s_freq src_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct skl_up_down_mixer_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct skl_base_cfg base_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum skl_ch_cfg out_ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* This should be set to 1 if user coefficients are required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 coeff_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Pass the user coeff in this array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct skl_algo_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct skl_base_cfg base_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) char params[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct skl_base_outfmt_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct skl_base_cfg base_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct skl_audio_data_format out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum skl_dma_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) union skl_ssp_dma_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 time_slot_index:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 i2s_instance:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } dma_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) union skl_connector_node_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 vindex:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 dma_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 rsvd:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct skl_module_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 interleaving_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct skl_module_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct skl_mod_inst_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 mod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 inst_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct skl_uuid_inst_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 inst_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) guid_t mod_uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct skl_kpb_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 num_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct skl_mod_inst_map map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct skl_uuid_inst_map map_uuid[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct skl_module_inst_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) guid_t mod_uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 instance_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum skl_module_pin_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SKL_PIN_UNBIND = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SKL_PIN_BIND_DONE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct skl_module_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct skl_module_inst_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool is_dynamic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum skl_module_pin_state pin_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct skl_module_cfg *tgt_mcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct skl_specific_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 caps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum skl_pipe_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SKL_PIPE_INVALID = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SKL_PIPE_CREATED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SKL_PIPE_PAUSED = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SKL_PIPE_STARTED = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SKL_PIPE_RESET = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct skl_pipe_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct skl_pipe_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 host_dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 link_dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 s_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 linktype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) snd_pcm_format_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int link_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int host_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int link_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct skl_pipe_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct skl_pipe_mcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct skl_path_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct skl_pipe_fmt in_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct skl_pipe_fmt out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct skl_pipe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 ppl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 pipe_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 conn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 memory_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 lp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct skl_pipe_params *p_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) enum skl_pipe_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 cur_config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 nr_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct list_head w_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bool passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 pipe_config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum skl_module_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SKL_MODULE_UNINIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SKL_MODULE_LOADED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SKL_MODULE_INIT_DONE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SKL_MODULE_BIND_DONE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SKL_MODULE_UNLOADED = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) enum d0i3_capability {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SKL_D0I3_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SKL_D0I3_STREAMING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SKL_D0I3_NON_STREAMING = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct skl_module_pin_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct skl_module_fmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct skl_module_iface {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 nr_in_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 nr_out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct skl_module_pin_resources {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 pin_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct skl_module_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 is_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 dma_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 cpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 nr_input_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 nr_output_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct skl_module_pin_resources input[MAX_IN_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct skl_module_pin_resources output[MAX_OUT_QUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct skl_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) guid_t uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 loadable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 input_pin_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 output_pin_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 max_input_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 max_output_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 nr_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 nr_interfaces;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct skl_module_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 guid[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct skl_module_inst_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct skl_module *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bool homogenous_inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bool homogenous_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u8 max_in_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 max_out_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 in_queue_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 out_queue_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 in_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 out_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 is_loadable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 time_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 dmic_ch_combo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 dmic_ch_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 converter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 vbus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) enum d0i3_capability d0i3_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 dma_buffer_size; /* in milli seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct skl_module_pin *m_in_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct skl_module_pin *m_out_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) enum skl_module_type m_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) enum skl_hw_conn_type hw_conn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) enum skl_module_state m_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct skl_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct skl_specific_cfg formats_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct skl_algo_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) char *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct skl_pipeline {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct skl_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct skl_module_deferred_bind {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct skl_module_cfg *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct skl_module_cfg *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct skl_mic_sel_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u16 mic_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum skl_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SKL_CH_MONO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SKL_CH_STEREO = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SKL_CH_TRIO = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SKL_CH_QUATRO = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static inline struct skl_dev *get_skl_ctx(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int skl_tplg_be_update_params(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct skl_pipe_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 caps_size, u32 node_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct skl_pipe_params *params, int stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int skl_tplg_init(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct hdac_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void skl_tplg_exit(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct hdac_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct snd_soc_dai *dai, int stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int skl_tplg_update_pipe_params(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *src_mcfg, struct skl_module_cfg *dst_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *src_mcfg, struct skl_module_cfg *dst_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int skl_set_module_params(struct skl_dev *skl, u32 *params, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 param_id, struct skl_module_cfg *mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int skl_get_module_params(struct skl_dev *skl, u32 *params, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 param_id, struct skl_module_cfg *mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) enum skl_bitdepth skl_get_bit_depth(int params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int skl_pcm_host_dma_prepare(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct skl_pipe_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int skl_pcm_link_dma_prepare(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct skl_pipe_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int skl_dai_load(struct snd_soc_component *cmp, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct snd_soc_dai_driver *dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct snd_soc_dapm_widget *w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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