^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-topology.c - Implements Platform component ALSA controls/widget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014-2015 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/uuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/intel-nhlt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/soc-acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/soc-topology.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <uapi/sound/snd_sst_tokens.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <uapi/sound/skl-tplg-interface.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "skl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "skl-sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "skl-topology.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SKL_CH_FIXUP_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SKL_RATE_FIXUP_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SKL_FMT_FIXUP_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SKL_IN_DIR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SKL_PIN_COUNT_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const int mic_mono_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0, 1, 2, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const int mic_stereo_list[][SKL_CH_STEREO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {0, 1}, {0, 2}, {0, 3}, {1, 2}, {1, 3}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const int mic_trio_list[][SKL_CH_TRIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {0, 1, 2}, {0, 1, 3}, {0, 2, 3}, {1, 2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const int mic_quatro_list[][SKL_CH_QUATRO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {0, 1, 2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHECK_HW_PARAMS(ch, freq, bps, prm_ch, prm_freq, prm_bps) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ((ch == prm_ch) && (bps == prm_bps) && (freq == prm_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct skl_d0i3_data *d0i3 = &skl->d0i3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) switch (caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case SKL_D0I3_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) d0i3->non_d0i3++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case SKL_D0I3_STREAMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) d0i3->streaming++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case SKL_D0I3_NON_STREAMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) d0i3->non_streaming++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct skl_d0i3_data *d0i3 = &skl->d0i3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) switch (caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case SKL_D0I3_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) d0i3->non_d0i3--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case SKL_D0I3_STREAMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) d0i3->streaming--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case SKL_D0I3_NON_STREAMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) d0i3->non_streaming--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * ignore. This helpers checks if the SKL driver handles this widget type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (w->dapm->dev != dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) switch (w->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case snd_soc_dapm_dai_link:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case snd_soc_dapm_dai_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case snd_soc_dapm_aif_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case snd_soc_dapm_aif_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case snd_soc_dapm_dai_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case snd_soc_dapm_switch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case snd_soc_dapm_output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case snd_soc_dapm_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void skl_dump_mconfig(struct skl_dev *skl, struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct skl_module_iface *iface = &mcfg->module->formats[mcfg->fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_dbg(skl->dev, "Dumping config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_dbg(skl->dev, "Input Format:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_dbg(skl->dev, "channels = %d\n", iface->inputs[0].fmt.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_dbg(skl->dev, "s_freq = %d\n", iface->inputs[0].fmt.s_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_dbg(skl->dev, "ch_cfg = %d\n", iface->inputs[0].fmt.ch_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(skl->dev, "valid bit depth = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) iface->inputs[0].fmt.valid_bit_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_dbg(skl->dev, "Output Format:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_dbg(skl->dev, "channels = %d\n", iface->outputs[0].fmt.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_dbg(skl->dev, "s_freq = %d\n", iface->outputs[0].fmt.s_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_dbg(skl->dev, "valid bit depth = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) iface->outputs[0].fmt.valid_bit_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_dbg(skl->dev, "ch_cfg = %d\n", iface->outputs[0].fmt.ch_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int slot_map = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int start_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 0; i < chs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * For 2 channels with starting slot as 0, slot map will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * look like 0xFFFFFF10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) start_slot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fmt->ch_map = slot_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void skl_tplg_update_params(struct skl_module_fmt *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct skl_pipe_params *params, int fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (fixup & SKL_RATE_FIXUP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fmt->s_freq = params->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (fixup & SKL_CH_FIXUP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) fmt->channels = params->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) skl_tplg_update_chmap(fmt, fmt->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (fixup & SKL_FMT_FIXUP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 16 bit is 16 bit container whereas 24 bit is in 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * container so update bit depth accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (fmt->valid_bit_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case SKL_DEPTH_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) fmt->bit_depth = fmt->valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) fmt->bit_depth = SKL_DEPTH_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * A pipeline may have modules which impact the pcm parameters, like SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * channel converter, format converter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * We need to calculate the output params by applying the 'fixup'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Topology will tell driver which type of fixup is to be applied by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * supplying the fixup mask, so based on that we calculate the output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Now In FE the pcm hw_params is source/target format. Same is applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * for BE with its hw_params invoked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * here based on FE, BE pipeline and direction we calculate the input and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * outfix and then apply that for a module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct skl_pipe_params *params, bool is_fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int in_fixup, out_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct skl_module_fmt *in_fmt, *out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Fixups will be applied to pin 0 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) in_fmt = &m_cfg->module->formats[m_cfg->fmt_idx].inputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) out_fmt = &m_cfg->module->formats[m_cfg->fmt_idx].outputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (is_fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) in_fixup = m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) out_fixup = (~m_cfg->converter) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) out_fixup = m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) in_fixup = (~m_cfg->converter) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (is_fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) out_fixup = m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) in_fixup = (~m_cfg->converter) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) in_fixup = m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) out_fixup = (~m_cfg->converter) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) m_cfg->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) skl_tplg_update_params(in_fmt, params, in_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) skl_tplg_update_params(out_fmt, params, out_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * A module needs input and output buffers, which are dependent upon pcm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * params, so once we have calculate params, we need buffer calculation as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void skl_tplg_update_buffer_size(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int multiplier = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct skl_module_fmt *in_fmt, *out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct skl_module_res *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Since fixups is applied to pin 0 only, ibs, obs needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * change for pin 0 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) res = &mcfg->module->resources[mcfg->res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) in_fmt = &mcfg->module->formats[mcfg->fmt_idx].inputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) out_fmt = &mcfg->module->formats[mcfg->fmt_idx].outputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) multiplier = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) res->ibs = DIV_ROUND_UP(in_fmt->s_freq, 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) in_fmt->channels * (in_fmt->bit_depth >> 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) res->obs = DIV_ROUND_UP(out_fmt->s_freq, 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) out_fmt->channels * (out_fmt->bit_depth >> 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u8 skl_tplg_be_dev_type(int dev_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch (dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case SKL_DEVICE_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = NHLT_DEVICE_BT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case SKL_DEVICE_DMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = NHLT_DEVICE_DMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case SKL_DEVICE_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = NHLT_DEVICE_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = NHLT_DEVICE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct skl_module_cfg *m_cfg = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int link_type, dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 ch, s_freq, s_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct nhlt_specific_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 dev_type = skl_tplg_be_dev_type(m_cfg->dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int fmt_idx = m_cfg->fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct skl_module_iface *m_iface = &m_cfg->module->formats[fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* check if we already have blob */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (m_cfg->formats_config.caps_size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_dbg(skl->dev, "Applying default cfg blob\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) switch (m_cfg->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case SKL_DEVICE_DMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) link_type = NHLT_LINK_DMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dir = SNDRV_PCM_STREAM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) s_freq = m_iface->inputs[0].fmt.s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) s_fmt = m_iface->inputs[0].fmt.bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ch = m_iface->inputs[0].fmt.channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case SKL_DEVICE_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) link_type = NHLT_LINK_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dir = SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) s_freq = m_iface->outputs[0].fmt.s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) s_fmt = m_iface->outputs[0].fmt.bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ch = m_iface->outputs[0].fmt.channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dir = SNDRV_PCM_STREAM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) s_freq = m_iface->inputs[0].fmt.s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) s_fmt = m_iface->inputs[0].fmt.bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ch = m_iface->inputs[0].fmt.channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* update the blob based on virtual bus_id and default params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) s_fmt, ch, s_freq, dir, dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) m_cfg->formats_config.caps_size = cfg->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) m_cfg->formats_config.caps = (u32 *) &cfg->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(skl->dev, "Blob NULL for id %x type %d dirn %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) m_cfg->vbus_id, link_type, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(skl->dev, "PCM: ch %d, freq %d, fmt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ch, s_freq, s_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct skl_module_cfg *m_cfg = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct skl_pipe_params *params = m_cfg->pipe->p_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int p_conn_type = m_cfg->pipe->conn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bool is_fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!m_cfg->params_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_dbg(skl->dev, "Mconfig for widget=%s BEFORE updation\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) w->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) skl_dump_mconfig(skl, m_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) is_fe = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) is_fe = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) skl_tplg_update_params_fixup(m_cfg, params, is_fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) skl_tplg_update_buffer_size(skl, m_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_dbg(skl->dev, "Mconfig for widget=%s AFTER updation\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) w->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) skl_dump_mconfig(skl, m_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * some modules can have multiple params set from user control and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * need to be set after module is initialized. If set_param flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * set module params will be done after module is initialised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const struct snd_kcontrol_new *k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct soc_bytes_ext *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct skl_algo_data *bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct skl_specific_cfg *sp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (mconfig->formats_config.caps_size > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mconfig->formats_config.set_params == SKL_PARAM_SET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sp_cfg = &mconfig->formats_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = skl_set_module_params(skl, sp_cfg->caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sp_cfg->caps_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sp_cfg->param_id, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) for (i = 0; i < w->num_kcontrols; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) k = &w->kcontrol_news[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sb = (void *) k->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) bc = (struct skl_algo_data *)sb->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (bc->set_params == SKL_PARAM_SET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = skl_set_module_params(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (u32 *)bc->params, bc->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bc->param_id, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * some module param can set from user control and this is required as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * when module is initailzed. if module param is required in init it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * identifed by set_param flag. if set_param flag is not set, then this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * parameter needs to set as part of module init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct snd_kcontrol_new *k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct soc_bytes_ext *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct skl_algo_data *bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = 0; i < w->num_kcontrols; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) k = &w->kcontrol_news[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) sb = (struct soc_bytes_ext *)k->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) bc = (struct skl_algo_data *)sb->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (bc->set_params != SKL_PARAM_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mconfig->formats_config.caps = (u32 *)bc->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mconfig->formats_config.caps_size = bc->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int skl_tplg_module_prepare(struct skl_dev *skl, struct skl_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct snd_soc_dapm_widget *w, struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) switch (mcfg->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case SKL_DEVICE_HDAHOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return skl_pcm_host_dma_prepare(skl->dev, pipe->p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case SKL_DEVICE_HDALINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return skl_pcm_link_dma_prepare(skl->dev, pipe->p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Inside a pipe instance, we can have various modules. These modules need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * skl_init_module() routine, so invoke that for all modules in a pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) skl_tplg_init_pipe_modules(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct skl_pipe_module *w_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 cfg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) list_for_each_entry(w_module, &pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) guid_t *uuid_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) w = w_module->w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* check if module ids are populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (mconfig->id.module_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_err(skl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "module %pUL id not populated\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (guid_t *)mconfig->guid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cfg_idx = mconfig->pipe->cur_config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mconfig->fmt_idx = mconfig->mod_cfg[cfg_idx].fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mconfig->res_idx = mconfig->mod_cfg[cfg_idx].res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (mconfig->module->loadable && skl->dsp->fw_ops.load_mod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = skl->dsp->fw_ops.load_mod(skl->dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mconfig->id.module_id, mconfig->guid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mconfig->m_state = SKL_MODULE_LOADED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* prepare the DMA if the module is gateway cpr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = skl_tplg_module_prepare(skl, pipe, w, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* update blob if blob is null for be with default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) skl_tplg_update_be_blob(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * apply fix/conversion to module params based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * FE/BE params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) skl_tplg_update_module_params(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uuid_mod = (guid_t *)mconfig->guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mconfig->id.pvt_id = skl_get_pvt_id(skl, uuid_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mconfig->id.instance_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (mconfig->id.pvt_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) skl_tplg_set_module_init_data(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = skl_dsp_get_core(skl->dsp, mconfig->core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(skl->dev, "Failed to wake up core %d ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mconfig->core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = skl_init_module(skl, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) skl_put_pvt_id(skl, uuid_mod, &mconfig->id.pvt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = skl_tplg_set_module_params(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) skl_dsp_put_core(skl->dsp, mconfig->core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int skl_tplg_unload_pipe_modules(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct skl_pipe_module *w_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) list_for_each_entry(w_module, &pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) guid_t *uuid_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mconfig = w_module->w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uuid_mod = (guid_t *)mconfig->guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (mconfig->module->loadable && skl->dsp->fw_ops.unload_mod &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mconfig->m_state > SKL_MODULE_UNINIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = skl->dsp->fw_ops.unload_mod(skl->dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mconfig->id.module_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) skl_put_pvt_id(skl, uuid_mod, &mconfig->id.pvt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = skl_dsp_put_core(skl->dsp, mconfig->core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* don't return; continue with other modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(skl->dev, "Failed to sleep core %d ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mconfig->core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* no modules to unload in this path, so return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static bool skl_tplg_is_multi_fmt(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct skl_pipe_fmt *cur_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct skl_pipe_fmt *next_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (pipe->nr_cfgs <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) for (i = 0; i < pipe->nr_cfgs - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (pipe->direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cur_fmt = &pipe->configs[i].out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) next_fmt = &pipe->configs[i + 1].out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cur_fmt = &pipe->configs[i].in_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) next_fmt = &pipe->configs[i + 1].in_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!CHECK_HW_PARAMS(cur_fmt->channels, cur_fmt->freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cur_fmt->bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) next_fmt->channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) next_fmt->freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) next_fmt->bps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Here, we select pipe format based on the pipe type and pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * direction to determine the current config index for the pipeline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * The config index is then used to select proper module resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Intermediate pipes currently have a fixed format hence we select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * 0th configuratation by default for such pipes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) skl_tplg_get_pipe_config(struct skl_dev *skl, struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct skl_pipe *pipe = mconfig->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct skl_pipe_params *params = pipe->p_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct skl_path_config *pconfig = &pipe->configs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct skl_pipe_fmt *fmt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) bool in_fmt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (pipe->nr_cfgs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pipe->cur_config_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (skl_tplg_is_multi_fmt(skl, pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pipe->cur_config_idx = pipe->pipe_config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pipe->memory_pages = pconfig->mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_dbg(skl->dev, "found pipe config idx:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pipe->cur_config_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (pipe->conn_type == SKL_PIPE_CONN_TYPE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_dbg(skl->dev, "No conn_type detected, take 0th config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pipe->cur_config_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pipe->memory_pages = pconfig->mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if ((pipe->conn_type == SKL_PIPE_CONN_TYPE_FE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pipe->direction == SNDRV_PCM_STREAM_PLAYBACK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (pipe->conn_type == SKL_PIPE_CONN_TYPE_BE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pipe->direction == SNDRV_PCM_STREAM_CAPTURE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) in_fmt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) for (i = 0; i < pipe->nr_cfgs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pconfig = &pipe->configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (in_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) fmt = &pconfig->in_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) fmt = &pconfig->out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (CHECK_HW_PARAMS(params->ch, params->s_freq, params->s_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) fmt->channels, fmt->freq, fmt->bps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pipe->cur_config_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pipe->memory_pages = pconfig->mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_dbg(skl->dev, "Using pipe config: %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(skl->dev, "Invalid pipe config: %d %d %d for pipe: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) params->ch, params->s_freq, params->s_fmt, pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * need create the pipeline. So we do following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * - Create the pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * - Initialize the modules in pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * - finally bind all modules together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct skl_pipe_module *w_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct skl_pipe *s_pipe = mconfig->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct skl_module_cfg *src_module = NULL, *dst_module, *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct skl_module_deferred_bind *modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = skl_tplg_get_pipe_config(skl, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Create a list of modules for pipe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * This list contains modules from source to sink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = skl_create_pipeline(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Init all pipe modules from source to sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = skl_tplg_init_pipe_modules(skl, s_pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Bind modules from source to sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) list_for_each_entry(w_module, &s_pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dst_module = w_module->w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (src_module == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) src_module = dst_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = skl_bind_modules(skl, src_module, dst_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) src_module = dst_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * When the destination module is initialized, check for these modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * in deferred bind list. If found, bind them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) list_for_each_entry(w_module, &s_pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (list_empty(&skl->bind_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) list_for_each_entry(modules, &skl->bind_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) module = w_module->w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (modules->dst == module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) skl_bind_modules(skl, modules->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) modules->dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int skl_fill_sink_instance_id(struct skl_dev *skl, u32 *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int size, struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int i, pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (mcfg->m_type == SKL_MODULE_TYPE_KPB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct skl_kpb_params *kpb_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (struct skl_kpb_params *)params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct skl_mod_inst_map *inst = kpb_params->u.map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0; i < kpb_params->num_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pvt_id = skl_get_pvt_instance_id_map(skl, inst->mod_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) inst->inst_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (pvt_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) inst->inst_id = pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) inst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * Some modules require params to be set after the module is bound to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * all pins connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * The module provider initializes set_param flag for such modules and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * send params after binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct skl_module_cfg *mcfg, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) const struct snd_kcontrol_new *k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct soc_bytes_ext *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct skl_algo_data *bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct skl_specific_cfg *sp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * check all out/in pins are in bind state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * if so set the module param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) for (i = 0; i < mcfg->module->max_output_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) for (i = 0; i < mcfg->module->max_input_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (mconfig->formats_config.caps_size > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mconfig->formats_config.set_params == SKL_PARAM_BIND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) sp_cfg = &mconfig->formats_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = skl_set_module_params(skl, sp_cfg->caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) sp_cfg->caps_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) sp_cfg->param_id, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) for (i = 0; i < w->num_kcontrols; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) k = &w->kcontrol_news[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) sb = (void *) k->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) bc = (struct skl_algo_data *)sb->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (bc->set_params == SKL_PARAM_BIND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) params = kmemdup(bc->params, bc->max, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) skl_fill_sink_instance_id(skl, params, bc->max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = skl_set_module_params(skl, params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) bc->max, bc->param_id, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) kfree(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int skl_get_module_id(struct skl_dev *skl, guid_t *uuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct uuid_module *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) list_for_each_entry(module, &skl->uuid_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (guid_equal(uuid, &module->uuid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return module->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int skl_tplg_find_moduleid_from_uuid(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) const struct snd_kcontrol_new *k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct soc_bytes_ext *sb = (void *) k->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct skl_kpb_params *uuid_params, *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int i, size, module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (bc->set_params == SKL_PARAM_BIND && bc->max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) uuid_params = (struct skl_kpb_params *)bc->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) size = struct_size(params, u.map, uuid_params->num_modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) params = devm_kzalloc(bus->dev, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) params->num_modules = uuid_params->num_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) for (i = 0; i < uuid_params->num_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) module_id = skl_get_module_id(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &uuid_params->u.map_uuid[i].mod_uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (module_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) devm_kfree(bus->dev, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) params->u.map[i].mod_id = module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) params->u.map[i].inst_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uuid_params->u.map_uuid[i].inst_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) devm_kfree(bus->dev, bc->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) bc->params = (char *)params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) bc->max = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Retrieve the module id from UUID mentioned in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * post bind params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct snd_soc_dapm_widget *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Post bind params are used for only for KPB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * to set copier instances to drain the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * in fast mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (mconfig->m_type != SKL_MODULE_TYPE_KPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) for (i = 0; i < w->num_kcontrols; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if ((w->kcontrol_news[i].access &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) (skl_tplg_find_moduleid_from_uuid(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &w->kcontrol_news[i]) < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_err(skl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "%s: invalid kpb post bind params\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int skl_tplg_module_add_deferred_bind(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct skl_module_cfg *src, struct skl_module_cfg *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct skl_module_deferred_bind *m_list, *modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* only supported for module with static pin connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) for (i = 0; i < dst->module->max_input_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct skl_module_pin *pin = &dst->m_in_pin[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (pin->is_dynamic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if ((pin->id.module_id == src->id.module_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (pin->id.instance_id == src->id.instance_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!list_empty(&skl->bind_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) list_for_each_entry(modules, &skl->bind_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (modules->src == src && modules->dst == dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) m_list = kzalloc(sizeof(*m_list), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (!m_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) m_list->src = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) m_list->dst = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) list_add(&m_list->node, &skl->bind_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct snd_soc_dapm_widget *src_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct skl_module_cfg *src_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct snd_soc_dapm_path *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct skl_module_cfg *sink_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) snd_soc_dapm_widget_for_each_sink_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!p->connect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_dbg(skl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "%s: src widget=%s\n", __func__, w->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_dbg(skl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "%s: sink widget=%s\n", __func__, p->sink->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) next_sink = p->sink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!is_skl_dsp_widget_type(p->sink, skl->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * here we will check widgets in sink pipelines, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * can be any widgets type and we are only interested if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * they are ones used for SKL so check that first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if ((p->sink->priv != NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) is_skl_dsp_widget_type(p->sink, skl->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) sink = p->sink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) sink_mconfig = sink->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * Modules other than PGA leaf can be connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * directly or via switch to a module in another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * pipeline. EX: reference path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * when the path is enabled, the dst module that needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * to be bound may not be initialized. if the module is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * not initialized, add these modules in the deferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * bind list and when the dst module is initialised,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * bind this module to the dst_module in deferred list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (((src_mconfig->m_state == SKL_MODULE_INIT_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) && (sink_mconfig->m_state == SKL_MODULE_UNINIT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ret = skl_tplg_module_add_deferred_bind(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) src_mconfig, sink_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) sink_mconfig->m_state == SKL_MODULE_UNINIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Bind source to sink, mixin is always source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = skl_bind_modules(skl, src_mconfig, sink_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* set module params after bind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) skl_tplg_set_module_bind_params(src_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) src_mconfig, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) skl_tplg_set_module_bind_params(sink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) sink_mconfig, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Start sinks pipe first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (sink_mconfig->pipe->conn_type !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) SKL_PIPE_CONN_TYPE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret = skl_run_pipe(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) sink_mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (!sink && next_sink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * we need to do following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * - Bind to sink pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Since the sink pipes can be running and we don't get mixer event on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * connect for already running mixer, we need to find the sink pipes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * here and bind to them. This way dynamic connect works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * - Start sink pipeline, if not running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * - Then run current pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct skl_module_cfg *src_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) src_mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * find which sink it is connected to, bind with the sink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * if sink is not started, start sink pipe first, then start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * this pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Start source pipe last after starting all sinks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return skl_run_pipe(skl, src_mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct snd_soc_dapm_widget *w, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct snd_soc_dapm_path *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct snd_soc_dapm_widget *src_w = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) snd_soc_dapm_widget_for_each_source_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) src_w = p->source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (!p->connect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dev_dbg(skl->dev, "sink widget=%s\n", w->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dev_dbg(skl->dev, "src widget=%s\n", p->source->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * here we will check widgets in sink pipelines, so that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * be any widgets type and we are only interested if they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * ones used for SKL so check that first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if ((p->source->priv != NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) is_skl_dsp_widget_type(p->source, skl->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return p->source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (src_w != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return skl_get_src_dsp_widget(src_w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * in the Post-PMU event of mixer we need to do following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * - Check if this pipe is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * - if not, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * - bind this pipeline to its source pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * if source pipe is already running, this means it is a dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * connection and we need to bind only to that pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * - start this pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct snd_soc_dapm_widget *source, *sink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct skl_module_cfg *src_mconfig, *sink_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int src_pipe_started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) sink = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) sink_mconfig = sink->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * If source pipe is already started, that means source is driving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * one more sink before this sink got connected, Since source is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * started, bind this sink to source and start this pipe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) source = skl_get_src_dsp_widget(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (source != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) src_mconfig = source->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) sink_mconfig = sink->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) src_pipe_started = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * check pipe state, then no need to bind or start the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) src_pipe_started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (src_pipe_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = skl_bind_modules(skl, src_mconfig, sink_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* set module params after bind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) skl_tplg_set_module_bind_params(source, src_mconfig, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) skl_tplg_set_module_bind_params(sink, sink_mconfig, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = skl_run_pipe(skl, sink_mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * in the Pre-PMD event of mixer we need to do following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * - Stop the pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * - find the source connections and remove that from dapm_path_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * - unbind with source pipelines if still connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct skl_module_cfg *src_mconfig, *sink_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) sink_mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Stop the pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = skl_stop_pipe(skl, sink_mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) for (i = 0; i < sink_mconfig->module->max_input_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (!src_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = skl_unbind_modules(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) src_mconfig, sink_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * in the Post-PMD event of mixer we need to do following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * - Unbind the modules within the pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * - Delete the pipeline (modules are not required to be explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * deleted, pipeline delete is enough here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct skl_pipe_module *w_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct skl_module_cfg *src_module = NULL, *dst_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct skl_pipe *s_pipe = mconfig->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct skl_module_deferred_bind *modules, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (s_pipe->state == SKL_PIPE_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) list_for_each_entry(w_module, &s_pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (list_empty(&skl->bind_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) src_module = w_module->w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * When the destination module is deleted, Unbind the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * modules from deferred bind list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (modules->dst == src_module) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) skl_unbind_modules(skl, modules->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) modules->dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * When the source module is deleted, remove this entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * from the deferred bind list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (modules->src == src_module) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) list_del(&modules->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) modules->src = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) modules->dst = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) kfree(modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) list_for_each_entry(w_module, &s_pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dst_module = w_module->w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (src_module == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) src_module = dst_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) skl_unbind_modules(skl, src_module, dst_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) src_module = dst_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) skl_delete_pipe(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) list_for_each_entry(w_module, &s_pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) src_module = w_module->w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) src_module->m_state = SKL_MODULE_UNINIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return skl_tplg_unload_pipe_modules(skl, s_pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * in the Post-PMD event of PGA we need to do following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * - Stop the pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * - In source pipe is connected, unbind with source pipelines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct skl_module_cfg *src_mconfig, *sink_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) src_mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* Stop the pipe since this is a mixin module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = skl_stop_pipe(skl, src_mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) for (i = 0; i < src_mconfig->module->max_output_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (!sink_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * This is a connecter and if path is found that means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * unbind between source and sink has not happened yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = skl_unbind_modules(skl, src_mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) sink_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * second one is required that is created as another pipe entity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * The mixer is responsible for pipe management and represent a pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct snd_kcontrol *k, int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct snd_soc_dapm_context *dapm = w->dapm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct skl_dev *skl = get_skl_ctx(dapm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) case SND_SOC_DAPM_PRE_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) case SND_SOC_DAPM_POST_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) case SND_SOC_DAPM_PRE_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case SND_SOC_DAPM_POST_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * In modelling, we assumed rest of the modules in pipeline are PGA. But we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * the sink when it is running (two FE to one BE or one FE to two BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * scenarios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct snd_kcontrol *k, int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct snd_soc_dapm_context *dapm = w->dapm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct skl_dev *skl = get_skl_ctx(dapm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) case SND_SOC_DAPM_PRE_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) case SND_SOC_DAPM_POST_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return skl_tplg_pga_dapm_post_pmd_event(w, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static int skl_tplg_multi_config_set_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct snd_ctl_elem_value *ucontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) bool is_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct hdac_bus *bus = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct skl_pipeline *ppl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct skl_pipe *pipe = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) u32 *pipe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (!ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (is_set && ucontrol->value.enumerated.item[0] > ec->items)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) pipe_id = ec->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) list_for_each_entry(ppl, &skl->ppl_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (ppl->pipe->ppl_id == *pipe_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pipe = ppl->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (!pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (is_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) pipe->pipe_config_idx = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ucontrol->value.enumerated.item[0] = pipe->pipe_config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int skl_tplg_multi_config_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return skl_tplg_multi_config_set_get(kcontrol, ucontrol, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static int skl_tplg_multi_config_set(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return skl_tplg_multi_config_set_get(kcontrol, ucontrol, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static int skl_tplg_multi_config_get_dmic(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return skl_tplg_multi_config_set_get(kcontrol, ucontrol, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static int skl_tplg_multi_config_set_dmic(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return skl_tplg_multi_config_set_get(kcontrol, ucontrol, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) unsigned int __user *data, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct soc_bytes_ext *sb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) (struct soc_bytes_ext *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct skl_dev *skl = get_skl_ctx(w->dapm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (w->power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) skl_get_module_params(skl, (u32 *)bc->params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) bc->size, bc->param_id, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* decrement size for TLV header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) size -= 2 * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* check size as we don't want to send kernel data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (size > bc->max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) size = bc->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (bc->params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (copy_to_user(data, &bc->param_id, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (copy_to_user(data + 1, &size, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (copy_to_user(data + 2, bc->params, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define SKL_PARAM_VENDOR_ID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) const unsigned int __user *data, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct soc_bytes_ext *sb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) (struct soc_bytes_ext *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct skl_dev *skl = get_skl_ctx(w->dapm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (ac->params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (size > ac->max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ac->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (copy_from_user(ac->params, data, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (w->power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return skl_set_module_params(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) (u32 *)ac->params, ac->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ac->param_id, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static int skl_tplg_mic_control_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) u32 ch_type = *((u32 *)ec->dobj.private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (mconfig->dmic_ch_type == ch_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) mconfig->dmic_ch_combo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ucontrol->value.enumerated.item[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static int skl_fill_mic_sel_params(struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct skl_mic_sel_config *mic_cfg, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct skl_specific_cfg *sp_cfg = &mconfig->formats_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) sp_cfg->caps_size = sizeof(struct skl_mic_sel_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) sp_cfg->set_params = SKL_PARAM_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) sp_cfg->param_id = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (!sp_cfg->caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) sp_cfg->caps = devm_kzalloc(dev, sp_cfg->caps_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (!sp_cfg->caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) mic_cfg->mic_switch = SKL_MIC_SEL_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) mic_cfg->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) memcpy(sp_cfg->caps, mic_cfg, sp_cfg->caps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int skl_tplg_mic_control_set(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct skl_module_cfg *mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct skl_mic_sel_config mic_cfg = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) u32 ch_type = *((u32 *)ec->dobj.private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) const int *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) u8 in_ch, out_ch, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) mconfig->dmic_ch_type = ch_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) mconfig->dmic_ch_combo_index = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* enum control index 0 is INVALID, so no channels to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (mconfig->dmic_ch_combo_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* No valid channel selection map for index 0, so offset by 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) index = mconfig->dmic_ch_combo_index - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) switch (ch_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) case SKL_CH_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (mconfig->dmic_ch_combo_index > ARRAY_SIZE(mic_mono_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) list = &mic_mono_list[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) case SKL_CH_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (mconfig->dmic_ch_combo_index > ARRAY_SIZE(mic_stereo_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) list = mic_stereo_list[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) case SKL_CH_TRIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (mconfig->dmic_ch_combo_index > ARRAY_SIZE(mic_trio_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) list = mic_trio_list[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) case SKL_CH_QUATRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (mconfig->dmic_ch_combo_index > ARRAY_SIZE(mic_quatro_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) list = mic_quatro_list[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) dev_err(w->dapm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) "Invalid channel %d for mic_select module\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ch_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* channel type enum map to number of chanels for that type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) for (out_ch = 0; out_ch < ch_type; out_ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) in_ch = list[out_ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) mic_cfg.blob[out_ch][in_ch] = SKL_DEFAULT_MIC_SEL_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return skl_fill_mic_sel_params(mconfig, &mic_cfg, w->dapm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * Fill the dma id for host and link. In case of passthrough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * pipeline, this will both host and link in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * pipeline, so need to copy the link and host based on dev_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct skl_pipe *pipe = mcfg->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (pipe->passthru) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) switch (mcfg->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case SKL_DEVICE_HDALINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pipe->p_params->link_dma_id = params->link_dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pipe->p_params->link_index = params->link_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) pipe->p_params->link_bps = params->link_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case SKL_DEVICE_HDAHOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) pipe->p_params->host_dma_id = params->host_dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) pipe->p_params->host_bps = params->host_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) pipe->p_params->s_fmt = params->s_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) pipe->p_params->ch = params->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) pipe->p_params->s_freq = params->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) pipe->p_params->stream = params->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) pipe->p_params->format = params->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) memcpy(pipe->p_params, params, sizeof(*params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * The FE params are passed by hw_params of the DAI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * On hw_params, the params are stored in Gateway module of the FE and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * need to calculate the format in DSP module configuration, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * conversion is done here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) int skl_tplg_update_pipe_params(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct skl_module_res *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) struct skl_dev *skl = get_skl_ctx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) struct skl_module_fmt *format = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) u8 cfg_idx = mconfig->pipe->cur_config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) res = &mconfig->module->resources[mconfig->res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) skl_tplg_fill_dma_id(mconfig, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) mconfig->fmt_idx = mconfig->mod_cfg[cfg_idx].fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) mconfig->res_idx = mconfig->mod_cfg[cfg_idx].res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (skl->nr_modules)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) format = &mconfig->module->formats[mconfig->fmt_idx].inputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) format = &mconfig->module->formats[mconfig->fmt_idx].outputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* set the hw_params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) format->s_freq = params->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) format->channels = params->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * 16 bit is 16 bit container whereas 24 bit is in 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * container so update bit depth accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) switch (format->valid_bit_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) case SKL_DEPTH_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) format->bit_depth = format->valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) case SKL_DEPTH_24BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) case SKL_DEPTH_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) format->bit_depth = SKL_DEPTH_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dev_err(dev, "Invalid bit depth %x for pipe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) format->valid_bit_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) res->ibs = (format->s_freq / 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) (format->channels) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) (format->bit_depth >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) res->obs = (format->s_freq / 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) (format->channels) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) (format->bit_depth >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * Query the module config for the FE DAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * This is used to find the hw_params set for that DAI and apply to FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct skl_module_cfg *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct snd_soc_dapm_path *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) w = dai->playback_widget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) snd_soc_dapm_widget_for_each_sink_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (p->connect && p->sink->power &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) !is_skl_dsp_widget_type(p->sink, dai->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (p->sink->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dev_dbg(dai->dev, "set params for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) p->sink->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return p->sink->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) w = dai->capture_widget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) snd_soc_dapm_widget_for_each_source_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (p->connect && p->source->power &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) !is_skl_dsp_widget_type(p->source, dai->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (p->source->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) dev_dbg(dai->dev, "set params for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) p->source->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return p->source->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct snd_soc_dapm_path *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct skl_module_cfg *mconfig = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) snd_soc_dapm_widget_for_each_source_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (p->connect &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) (p->sink->id == snd_soc_dapm_aif_out) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) p->source->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) mconfig = p->source->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct snd_soc_dapm_path *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct skl_module_cfg *mconfig = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) snd_soc_dapm_widget_for_each_sink_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (p->connect &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) (p->source->id == snd_soc_dapm_aif_in) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) p->sink->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) mconfig = p->sink->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct skl_module_cfg *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) w = dai->playback_widget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) mconfig = skl_get_mconfig_pb_cpr(dai, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) w = dai->capture_widget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) mconfig = skl_get_mconfig_cap_cpr(dai, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static u8 skl_tplg_be_link_type(int dev_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) switch (dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) case SKL_DEVICE_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ret = NHLT_LINK_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) case SKL_DEVICE_DMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ret = NHLT_LINK_DMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) case SKL_DEVICE_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ret = NHLT_LINK_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) case SKL_DEVICE_HDALINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ret = NHLT_LINK_HDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ret = NHLT_LINK_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * Fill the BE gateway parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * The BE gateway expects a blob of parameters which are kept in the ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * The port can have multiple settings so pick based on the PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct nhlt_specific_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct skl_dev *skl = get_skl_ctx(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int link_type = skl_tplg_be_link_type(mconfig->dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) skl_tplg_fill_dma_id(mconfig, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (link_type == NHLT_LINK_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* update the blob based on virtual bus_id*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) params->s_fmt, params->ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) params->s_freq, params->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) mconfig->formats_config.caps_size = cfg->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) mconfig->formats_config.caps = (u32 *) &cfg->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) mconfig->vbus_id, link_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) params->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) params->ch, params->s_freq, params->s_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct snd_soc_dapm_path *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) snd_soc_dapm_widget_for_each_source_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (p->connect && is_skl_dsp_widget_type(p->source, dai->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) p->source->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ret = skl_tplg_be_fill_pipe_params(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) p->source->priv, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ret = skl_tplg_be_set_src_pipe_params(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) p->source, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct snd_soc_dapm_path *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) snd_soc_dapm_widget_for_each_sink_path(w, p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (p->connect && is_skl_dsp_widget_type(p->sink, dai->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) p->sink->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ret = skl_tplg_be_fill_pipe_params(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) p->sink->priv, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ret = skl_tplg_be_set_sink_pipe_params(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) dai, p->sink, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * BE hw_params can be a source parameters (capture) or sink parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * (playback). Based on sink and source we need to either find the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * list or the sink list and set the pipeline parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) int skl_tplg_be_update_params(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) w = dai->playback_widget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return skl_tplg_be_set_src_pipe_params(dai, w, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) w = dai->capture_widget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return skl_tplg_be_set_sink_pipe_params(dai, w, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {SKL_MIXER_EVENT, skl_tplg_mixer_event},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {SKL_VMIXER_EVENT, skl_tplg_mixer_event},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {SKL_PGA_EVENT, skl_tplg_pga_event},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) skl_tplg_tlv_control_set},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static const struct snd_soc_tplg_kcontrol_ops skl_tplg_kcontrol_ops[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .id = SKL_CONTROL_TYPE_MIC_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .get = skl_tplg_mic_control_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .put = skl_tplg_mic_control_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .id = SKL_CONTROL_TYPE_MULTI_IO_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .get = skl_tplg_multi_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .put = skl_tplg_multi_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .id = SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .get = skl_tplg_multi_config_get_dmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .put = skl_tplg_multi_config_set_dmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static int skl_tplg_fill_pipe_cfg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) struct skl_pipe *pipe, u32 tkn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) u32 tkn_val, int conf_idx, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct skl_pipe_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct skl_path_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case SKL_DIR_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) fmt = &pipe->configs[conf_idx].in_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) case SKL_DIR_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) fmt = &pipe->configs[conf_idx].out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) dev_err(dev, "Invalid direction: %d\n", dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) config = &pipe->configs[conf_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) switch (tkn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) case SKL_TKN_U32_CFG_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) fmt->freq = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) case SKL_TKN_U8_CFG_CHAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) fmt->channels = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) case SKL_TKN_U8_CFG_BPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) fmt->bps = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) case SKL_TKN_U32_PATH_MEM_PGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) config->mem_pages = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) dev_err(dev, "Invalid token config: %d\n", tkn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static int skl_tplg_fill_pipe_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct skl_pipe *pipe, u32 tkn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) u32 tkn_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) switch (tkn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) case SKL_TKN_U32_PIPE_CONN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) pipe->conn_type = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) case SKL_TKN_U32_PIPE_PRIORITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) pipe->pipe_priority = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) case SKL_TKN_U32_PIPE_MEM_PGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) pipe->memory_pages = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) case SKL_TKN_U32_PMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) pipe->lp_mode = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) case SKL_TKN_U32_PIPE_DIRECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) pipe->direction = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) case SKL_TKN_U32_NUM_CONFIGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) pipe->nr_cfgs = tkn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) dev_err(dev, "Token not handled %d\n", tkn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) * Add pipeline by parsing the relevant tokens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) * Return an existing pipe if the pipe already exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static int skl_tplg_add_pipe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct skl_module_cfg *mconfig, struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) struct snd_soc_tplg_vendor_value_elem *tkn_elem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct skl_pipeline *ppl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct skl_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct skl_pipe_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) list_for_each_entry(ppl, &skl->ppl_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (ppl->pipe->ppl_id == tkn_elem->value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) mconfig->pipe = ppl->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (!ppl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (!pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (!params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pipe->p_params = params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) pipe->ppl_id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) INIT_LIST_HEAD(&pipe->w_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ppl->pipe = pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) list_add(&ppl->node, &skl->ppl_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) mconfig->pipe = pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) mconfig->pipe->state = SKL_PIPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static int skl_tplg_get_uuid(struct device *dev, guid_t *guid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (uuid_tkn->token == SKL_TKN_UUID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) import_guid(guid, uuid_tkn->uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) dev_err(dev, "Not an UUID token %d\n", uuid_tkn->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static int skl_tplg_fill_pin(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct skl_module_pin *m_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) int pin_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) case SKL_TKN_U32_PIN_MOD_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) m_pin[pin_index].id.module_id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) case SKL_TKN_U32_PIN_INST_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) m_pin[pin_index].id.instance_id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) case SKL_TKN_UUID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ret = skl_tplg_get_uuid(dev, &m_pin[pin_index].id.mod_uuid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) (struct snd_soc_tplg_vendor_uuid_elem *)tkn_elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) dev_err(dev, "%d Not a pin token\n", tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * Parse for pin config specific tokens to fill up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * module private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static int skl_tplg_fill_pins_info(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) int dir, int pin_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) struct skl_module_pin *m_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) case SKL_DIR_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) m_pin = mconfig->m_in_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) case SKL_DIR_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) m_pin = mconfig->m_out_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dev_err(dev, "Invalid direction value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ret = skl_tplg_fill_pin(dev, tkn_elem, m_pin, pin_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) m_pin[pin_count].in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) * Fill up input/output module config format based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * on the direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static int skl_tplg_fill_fmt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) struct skl_module_fmt *dst_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) u32 tkn, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) switch (tkn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) case SKL_TKN_U32_FMT_CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dst_fmt->channels = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) case SKL_TKN_U32_FMT_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) dst_fmt->s_freq = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) case SKL_TKN_U32_FMT_BIT_DEPTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) dst_fmt->bit_depth = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) case SKL_TKN_U32_FMT_SAMPLE_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) dst_fmt->valid_bit_depth = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) case SKL_TKN_U32_FMT_CH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) dst_fmt->ch_cfg = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) case SKL_TKN_U32_FMT_INTERLEAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dst_fmt->interleaving_style = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) case SKL_TKN_U32_FMT_SAMPLE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) dst_fmt->sample_type = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) case SKL_TKN_U32_FMT_CH_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) dst_fmt->ch_map = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) dev_err(dev, "Invalid token %d\n", tkn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static int skl_tplg_widget_fill_fmt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) struct skl_module_iface *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) u32 tkn, u32 val, u32 dir, int fmt_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct skl_module_fmt *dst_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) case SKL_DIR_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) dst_fmt = &fmt->inputs[fmt_idx].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) case SKL_DIR_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) dst_fmt = &fmt->outputs[fmt_idx].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) dev_err(dev, "Invalid direction: %d\n", dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) return skl_tplg_fill_fmt(dev, dst_fmt, tkn, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static void skl_tplg_fill_pin_dynamic_val(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) struct skl_module_pin *mpin, u32 pin_count, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) for (i = 0; i < pin_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) mpin[i].is_dynamic = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * Resource table in the manifest has pin specific resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) * like pin and pin buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) static int skl_tplg_manifest_pin_res_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct skl_module_res *res, int pin_idx, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct skl_module_pin_resources *m_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) case SKL_DIR_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) m_pin = &res->input[pin_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) case SKL_DIR_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) m_pin = &res->output[pin_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) dev_err(dev, "Invalid pin direction: %d\n", dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) case SKL_TKN_MM_U32_RES_PIN_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) m_pin->pin_index = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) case SKL_TKN_MM_U32_PIN_BUF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) m_pin->buf_size = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) dev_err(dev, "Invalid token: %d\n", tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) * Fill module specific resources from the manifest's resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * table like CPS, DMA size, mem_pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static int skl_tplg_fill_res_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) struct skl_module_res *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) int pin_idx, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) int ret, tkn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) case SKL_TKN_MM_U32_DMA_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) res->dma_buffer_size = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) case SKL_TKN_MM_U32_CPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) res->cpc = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) case SKL_TKN_U32_MEM_PAGES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) res->is_pages = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) case SKL_TKN_U32_OBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) res->obs = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) case SKL_TKN_U32_IBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) res->ibs = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) case SKL_TKN_MM_U32_RES_PIN_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) case SKL_TKN_MM_U32_PIN_BUF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) ret = skl_tplg_manifest_pin_res_tkn(dev, tkn_elem, res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) pin_idx, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) case SKL_TKN_MM_U32_CPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) case SKL_TKN_U32_MAX_MCPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* ignore unused tokens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) dev_err(dev, "Not a res type token: %d", tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) tkn_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) return tkn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) * Parse tokens to fill up the module private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static int skl_tplg_get_token(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) struct skl_dev *skl, struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) int tkn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static int is_pipe_exists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) static int pin_index, dir, conf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) struct skl_module_iface *iface = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) struct skl_module_res *res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) int res_idx = mconfig->res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) int fmt_idx = mconfig->fmt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * If the manifest structure contains no modules, fill all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * the module data to 0th index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) * res_idx and fmt_idx are default set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (skl->nr_modules == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) res = &mconfig->module->resources[res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) iface = &mconfig->module->formats[fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if (tkn_elem->token > SKL_TKN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) case SKL_TKN_U8_IN_QUEUE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) mconfig->module->max_input_pins = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) case SKL_TKN_U8_OUT_QUEUE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) mconfig->module->max_output_pins = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) case SKL_TKN_U8_DYN_IN_PIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (!mconfig->m_in_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) mconfig->m_in_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) devm_kcalloc(dev, MAX_IN_QUEUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) sizeof(*mconfig->m_in_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (!mconfig->m_in_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin, MAX_IN_QUEUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) case SKL_TKN_U8_DYN_OUT_PIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (!mconfig->m_out_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) mconfig->m_out_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) devm_kcalloc(dev, MAX_IN_QUEUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) sizeof(*mconfig->m_in_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) if (!mconfig->m_out_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin, MAX_OUT_QUEUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) case SKL_TKN_U8_TIME_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) mconfig->time_slot = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) case SKL_TKN_U8_CORE_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) mconfig->core_id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) case SKL_TKN_U8_MOD_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) mconfig->m_type = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) case SKL_TKN_U8_DEV_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) mconfig->dev_type = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) case SKL_TKN_U8_HW_CONN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) mconfig->hw_conn_type = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) case SKL_TKN_U16_MOD_INST_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) mconfig->id.instance_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) case SKL_TKN_U32_MEM_PAGES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) case SKL_TKN_U32_MAX_MCPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) case SKL_TKN_U32_OBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) case SKL_TKN_U32_IBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) ret = skl_tplg_fill_res_tkn(dev, tkn_elem, res, pin_index, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) case SKL_TKN_U32_VBUS_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) mconfig->vbus_id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) case SKL_TKN_U32_PARAMS_FIXUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) mconfig->params_fixup = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) case SKL_TKN_U32_CONVERTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) mconfig->converter = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) case SKL_TKN_U32_D0I3_CAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) mconfig->d0i3_caps = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) case SKL_TKN_U32_PIPE_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) ret = skl_tplg_add_pipe(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) mconfig, skl, tkn_elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) if (ret == -EEXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) is_pipe_exists = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) return is_pipe_exists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) case SKL_TKN_U32_PIPE_CONFIG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) conf_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) case SKL_TKN_U32_PIPE_CONN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) case SKL_TKN_U32_PIPE_PRIORITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) case SKL_TKN_U32_PIPE_MEM_PGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) case SKL_TKN_U32_PMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) case SKL_TKN_U32_PIPE_DIRECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) case SKL_TKN_U32_NUM_CONFIGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (is_pipe_exists) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) tkn_elem->token, tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) case SKL_TKN_U32_PATH_MEM_PGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) case SKL_TKN_U32_CFG_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) case SKL_TKN_U8_CFG_CHAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case SKL_TKN_U8_CFG_BPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (mconfig->pipe->nr_cfgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ret = skl_tplg_fill_pipe_cfg(dev, mconfig->pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) tkn_elem->token, tkn_elem->value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) conf_idx, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) case SKL_TKN_CFG_MOD_RES_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) mconfig->mod_cfg[conf_idx].res_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) case SKL_TKN_CFG_MOD_FMT_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) mconfig->mod_cfg[conf_idx].fmt_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) * direction and the pin count. The first four bits represent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) * direction and next four the pin count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) case SKL_TKN_U32_DIR_PIN_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) pin_index = (tkn_elem->value &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) SKL_PIN_COUNT_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) case SKL_TKN_U32_FMT_CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) case SKL_TKN_U32_FMT_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) case SKL_TKN_U32_FMT_BIT_DEPTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) case SKL_TKN_U32_FMT_SAMPLE_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) case SKL_TKN_U32_FMT_CH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) case SKL_TKN_U32_FMT_INTERLEAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) case SKL_TKN_U32_FMT_SAMPLE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) case SKL_TKN_U32_FMT_CH_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) ret = skl_tplg_widget_fill_fmt(dev, iface, tkn_elem->token,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) tkn_elem->value, dir, pin_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) case SKL_TKN_U32_PIN_MOD_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) case SKL_TKN_U32_PIN_INST_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) case SKL_TKN_UUID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) ret = skl_tplg_fill_pins_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) mconfig, tkn_elem, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) pin_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) case SKL_TKN_U32_CAPS_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) mconfig->formats_config.caps_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) case SKL_TKN_U32_CAPS_SET_PARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) mconfig->formats_config.set_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) case SKL_TKN_U32_CAPS_PARAMS_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) mconfig->formats_config.param_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) case SKL_TKN_U32_PROC_DOMAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) mconfig->domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) case SKL_TKN_U32_DMA_BUF_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) mconfig->dma_buffer_size = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) case SKL_TKN_U8_IN_PIN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) case SKL_TKN_U8_OUT_PIN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) case SKL_TKN_U8_CONN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) dev_err(dev, "Token %d not handled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) tkn_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) return tkn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * Parse the vendor array for specific tokens to construct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) * module private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) static int skl_tplg_get_tokens(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) char *pvt_data, struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) struct skl_module_cfg *mconfig, int block_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) struct snd_soc_tplg_vendor_array *array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) struct snd_soc_tplg_vendor_value_elem *tkn_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) int tkn_count = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) int off = 0, tuple_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) bool is_module_guid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (block_size <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) while (tuple_size < block_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) switch (array->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) case SND_SOC_TPLG_TUPLE_TYPE_STRING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) dev_warn(dev, "no string tokens expected for skl tplg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) case SND_SOC_TPLG_TUPLE_TYPE_UUID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (is_module_guid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) ret = skl_tplg_get_uuid(dev, (guid_t *)mconfig->guid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) array->uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) is_module_guid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) ret = skl_tplg_get_token(dev, array->value, skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) tuple_size += sizeof(*array->uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) tkn_elem = array->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) tkn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) while (tkn_count <= (array->num_elems - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) ret = skl_tplg_get_token(dev, tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) skl, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) tkn_count = tkn_count + ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) tkn_elem++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) tuple_size += tkn_count * sizeof(*tkn_elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) * Every data block is preceded by a descriptor to read the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) * of data blocks, they type of the block and it's size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static int skl_tplg_get_desc_blocks(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) struct snd_soc_tplg_vendor_array *array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) struct snd_soc_tplg_vendor_value_elem *tkn_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) tkn_elem = array->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) case SKL_TKN_U8_NUM_BLOCKS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) case SKL_TKN_U8_BLOCK_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) case SKL_TKN_U16_BLOCK_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) return tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) dev_err(dev, "Invalid descriptor token %d\n", tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* Functions to parse private data from configuration file format v4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) * Add pipeline from topology binary into driver pipeline list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) * If already added we return that instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) * Otherwise we create a new instance and add into driver list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) static int skl_tplg_add_pipe_v4(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) struct skl_module_cfg *mconfig, struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) struct skl_dfw_v4_pipe *dfw_pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) struct skl_pipeline *ppl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) struct skl_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) struct skl_pipe_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) list_for_each_entry(ppl, &skl->ppl_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (ppl->pipe->ppl_id == dfw_pipe->pipe_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) mconfig->pipe = ppl->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (!ppl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) if (!pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) if (!params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) pipe->ppl_id = dfw_pipe->pipe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) pipe->memory_pages = dfw_pipe->memory_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) pipe->pipe_priority = dfw_pipe->pipe_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) pipe->conn_type = dfw_pipe->conn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) pipe->state = SKL_PIPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) pipe->p_params = params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) INIT_LIST_HEAD(&pipe->w_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) ppl->pipe = pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) list_add(&ppl->node, &skl->ppl_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) mconfig->pipe = pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) static void skl_fill_module_pin_info_v4(struct skl_dfw_v4_module_pin *dfw_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) struct skl_module_pin *m_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) bool is_dynamic, int max_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) for (i = 0; i < max_pin; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) m_pin[i].id.module_id = dfw_pin[i].module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) m_pin[i].id.instance_id = dfw_pin[i].instance_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) m_pin[i].in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) m_pin[i].is_dynamic = is_dynamic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) m_pin[i].pin_state = SKL_PIN_UNBIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static void skl_tplg_fill_fmt_v4(struct skl_module_pin_fmt *dst_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) struct skl_dfw_v4_module_fmt *src_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) int pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) for (i = 0; i < pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) dst_fmt[i].fmt.channels = src_fmt[i].channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) dst_fmt[i].fmt.s_freq = src_fmt[i].freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) dst_fmt[i].fmt.bit_depth = src_fmt[i].bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) dst_fmt[i].fmt.valid_bit_depth = src_fmt[i].valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) dst_fmt[i].fmt.ch_cfg = src_fmt[i].ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) dst_fmt[i].fmt.ch_map = src_fmt[i].ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) dst_fmt[i].fmt.interleaving_style =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) src_fmt[i].interleaving_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) dst_fmt[i].fmt.sample_type = src_fmt[i].sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) static int skl_tplg_get_pvt_data_v4(struct snd_soc_tplg_dapm_widget *tplg_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) struct skl_dev *skl, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) struct skl_dfw_v4_module *dfw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) (struct skl_dfw_v4_module *)tplg_w->priv.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) dev_dbg(dev, "Parsing Skylake v4 widget topology data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) ret = guid_parse(dfw->uuid, (guid_t *)mconfig->guid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) mconfig->id.module_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) mconfig->id.instance_id = dfw->instance_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) mconfig->module->resources[0].cpc = dfw->max_mcps / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) mconfig->module->resources[0].ibs = dfw->ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) mconfig->module->resources[0].obs = dfw->obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) mconfig->core_id = dfw->core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) mconfig->module->max_input_pins = dfw->max_in_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) mconfig->module->max_output_pins = dfw->max_out_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) mconfig->module->loadable = dfw->is_loadable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) skl_tplg_fill_fmt_v4(mconfig->module->formats[0].inputs, dfw->in_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) MAX_IN_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) skl_tplg_fill_fmt_v4(mconfig->module->formats[0].outputs, dfw->out_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) MAX_OUT_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) mconfig->params_fixup = dfw->params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) mconfig->converter = dfw->converter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) mconfig->m_type = dfw->module_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) mconfig->vbus_id = dfw->vbus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) mconfig->module->resources[0].is_pages = dfw->mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) ret = skl_tplg_add_pipe_v4(dev, mconfig, skl, &dfw->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) mconfig->dev_type = dfw->dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) mconfig->hw_conn_type = dfw->hw_conn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) mconfig->time_slot = dfw->time_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) mconfig->formats_config.caps_size = dfw->caps.caps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) mconfig->m_in_pin = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) MAX_IN_QUEUE, sizeof(*mconfig->m_in_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) if (!mconfig->m_in_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) mconfig->m_out_pin = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) MAX_OUT_QUEUE, sizeof(*mconfig->m_out_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (!mconfig->m_out_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) skl_fill_module_pin_info_v4(dfw->in_pin, mconfig->m_in_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) dfw->is_dynamic_in_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) mconfig->module->max_input_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) skl_fill_module_pin_info_v4(dfw->out_pin, mconfig->m_out_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) dfw->is_dynamic_out_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) mconfig->module->max_output_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) if (mconfig->formats_config.caps_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) mconfig->formats_config.set_params = dfw->caps.set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) mconfig->formats_config.param_id = dfw->caps.param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) mconfig->formats_config.caps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) devm_kzalloc(dev, mconfig->formats_config.caps_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) if (!mconfig->formats_config.caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) memcpy(mconfig->formats_config.caps, dfw->caps.caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) dfw->caps.caps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) * Parse the private data for the token and corresponding value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) * The private data can have multiple data blocks. So, a data block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) * is preceded by a descriptor for number of blocks and a descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) * for the type and size of the suceeding data block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) struct skl_dev *skl, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) struct snd_soc_tplg_vendor_array *array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) int num_blocks, block_size, block_type, off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) * v4 configuration files have a valid UUID at the start of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) * the widget's private data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) if (uuid_is_valid((char *)tplg_w->priv.data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) return skl_tplg_get_pvt_data_v4(tplg_w, skl, dev, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /* Read the NUM_DATA_BLOCKS descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) ret = skl_tplg_get_desc_blocks(dev, array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) num_blocks = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) while (num_blocks > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) array = (struct snd_soc_tplg_vendor_array *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) (tplg_w->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) ret = skl_tplg_get_desc_blocks(dev, array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) block_type = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) array = (struct snd_soc_tplg_vendor_array *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) (tplg_w->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) ret = skl_tplg_get_desc_blocks(dev, array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) block_size = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) array = (struct snd_soc_tplg_vendor_array *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) (tplg_w->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) data = (tplg_w->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) if (block_type == SKL_TYPE_TUPLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) ret = skl_tplg_get_tokens(dev, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) skl, mconfig, block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) --num_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) if (mconfig->formats_config.caps_size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) memcpy(mconfig->formats_config.caps, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) mconfig->formats_config.caps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) --num_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) ret = mconfig->formats_config.caps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) off += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) static void skl_clear_pin_config(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) struct snd_soc_dapm_widget *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) struct skl_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (!strncmp(w->dapm->component->name, component->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) strlen(component->name))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) pipe = mconfig->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) for (i = 0; i < mconfig->module->max_input_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) mconfig->m_in_pin[i].in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) for (i = 0; i < mconfig->module->max_output_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) mconfig->m_out_pin[i].in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) pipe->state = SKL_PIPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) mconfig->m_state = SKL_MODULE_UNINIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) void skl_cleanup_resources(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) struct snd_soc_component *soc_component = skl->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) struct snd_soc_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) if (soc_component == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) card = soc_component->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) if (!card || !card->instantiated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) list_for_each_entry(w, &card->widgets, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) if (is_skl_dsp_widget_type(w, skl->dev) && w->priv != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) skl_clear_pin_config(soc_component, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) skl_clear_module_cnt(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) * Topology core widget load callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) * This is used to save the private data for each widget which gives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) * information to the driver about module and pipeline parameters which DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) * FW expects like ids, resource values, formats etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static int skl_tplg_widget_load(struct snd_soc_component *cmpnt, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) struct snd_soc_tplg_dapm_widget *tplg_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) struct hdac_bus *bus = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) if (!tplg_w->priv.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) goto bind_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if (!mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) if (skl->nr_modules == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) mconfig->module = devm_kzalloc(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) sizeof(*mconfig->module), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) if (!mconfig->module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) w->priv = mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) * module binary can be loaded later, so set it to query when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) * module is load for a use case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) mconfig->id.module_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) /* Parse private data for tuples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) skl_debug_init_module(skl->debugfs, w, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) bind_event:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) if (tplg_w->event_type == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) dev_dbg(bus->dev, "ASoC: No event handler required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) ARRAY_SIZE(skl_tplg_widget_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) tplg_w->event_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) __func__, tplg_w->event_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) struct snd_soc_tplg_bytes_control *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) struct skl_algo_data *ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) struct skl_dfw_algo_data *dfw_ac =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) (struct skl_dfw_algo_data *)bc->priv.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (!ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /* Fill private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) ac->max = dfw_ac->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) ac->param_id = dfw_ac->param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) ac->set_params = dfw_ac->set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) ac->size = dfw_ac->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) if (ac->max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) ac->params = devm_kzalloc(dev, ac->max, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) if (!ac->params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) memcpy(ac->params, dfw_ac->params, ac->max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) be->dobj.private = ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) static int skl_init_enum_data(struct device *dev, struct soc_enum *se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) struct snd_soc_tplg_enum_control *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) if (ec->priv.size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) data = devm_kzalloc(dev, sizeof(ec->priv.size), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) memcpy(data, ec->priv.data, ec->priv.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) se->dobj.private = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) struct snd_kcontrol_new *kctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) struct snd_soc_tplg_ctl_hdr *hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) struct soc_bytes_ext *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) struct snd_soc_tplg_bytes_control *tplg_bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) struct snd_soc_tplg_enum_control *tplg_ec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) struct hdac_bus *bus = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) struct soc_enum *se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) switch (hdr->ops.info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) case SND_SOC_TPLG_CTL_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) tplg_bc = container_of(hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) struct snd_soc_tplg_bytes_control, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) sb = (struct soc_bytes_ext *)kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) if (tplg_bc->priv.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) return skl_init_algo_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) bus->dev, sb, tplg_bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) case SND_SOC_TPLG_CTL_ENUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) tplg_ec = container_of(hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) struct snd_soc_tplg_enum_control, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (kctl->access & SNDRV_CTL_ELEM_ACCESS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) se = (struct soc_enum *)kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (tplg_ec->priv.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) skl_init_enum_data(bus->dev, se, tplg_ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) * now that the control initializations are done, remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) * write permission for the DMIC configuration enums to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) * avoid conflicts between NHLT settings and user interaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) if (hdr->ops.get == SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) kctl->access = SNDRV_CTL_ELEM_ACCESS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) dev_dbg(bus->dev, "Control load not supported %d:%d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) hdr->ops.get, hdr->ops.put, hdr->ops.info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) struct snd_soc_tplg_vendor_string_elem *str_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) int tkn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) static int ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) switch (str_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) case SKL_TKN_STR_LIB_NAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) if (ref_count > skl->lib_count - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) ref_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) strncpy(skl->lib_info[ref_count].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) str_elem->string,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) ARRAY_SIZE(skl->lib_info[ref_count].name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) ref_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) dev_err(dev, "Not a string token %d\n", str_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) tkn_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) return tkn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) static int skl_tplg_get_str_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) struct snd_soc_tplg_vendor_array *array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) int tkn_count = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) struct snd_soc_tplg_vendor_string_elem *str_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) while (tkn_count < array->num_elems) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) str_elem++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) tkn_count = tkn_count + ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) return tkn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) static int skl_tplg_manifest_fill_fmt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) struct skl_module_iface *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) u32 dir, int fmt_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) struct skl_module_pin_fmt *dst_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) struct skl_module_fmt *mod_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) case SKL_DIR_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) dst_fmt = &fmt->inputs[fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) case SKL_DIR_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) dst_fmt = &fmt->outputs[fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) dev_err(dev, "Invalid direction: %d\n", dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) mod_fmt = &dst_fmt->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) case SKL_TKN_MM_U32_INTF_PIN_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) dst_fmt->id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) ret = skl_tplg_fill_fmt(dev, mod_fmt, tkn_elem->token,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) static int skl_tplg_fill_mod_info(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) struct skl_module *mod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) if (!mod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) case SKL_TKN_U8_IN_PIN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) mod->input_pin_type = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) case SKL_TKN_U8_OUT_PIN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) mod->output_pin_type = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) case SKL_TKN_U8_IN_QUEUE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) mod->max_input_pins = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) case SKL_TKN_U8_OUT_QUEUE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) mod->max_output_pins = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) case SKL_TKN_MM_U8_NUM_RES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) mod->nr_resources = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) case SKL_TKN_MM_U8_NUM_INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) mod->nr_interfaces = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) dev_err(dev, "Invalid mod info token %d", tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) static int skl_tplg_get_int_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) struct snd_soc_tplg_vendor_value_elem *tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) int tkn_count = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static int mod_idx, res_val_idx, intf_val_idx, dir, pin_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) struct skl_module_res *res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) struct skl_module_iface *fmt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) struct skl_module *mod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) static struct skl_astate_param *astate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) static int astate_cfg_idx, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) if (skl->modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) mod = skl->modules[mod_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) res = &mod->resources[res_val_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) fmt = &mod->formats[intf_val_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) switch (tkn_elem->token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) case SKL_TKN_U32_LIB_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) skl->lib_count = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) case SKL_TKN_U8_NUM_MOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) skl->nr_modules = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) skl->modules = devm_kcalloc(dev, skl->nr_modules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) sizeof(*skl->modules), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) if (!skl->modules)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) for (i = 0; i < skl->nr_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) skl->modules[i] = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) sizeof(struct skl_module), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) if (!skl->modules[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) case SKL_TKN_MM_U8_MOD_IDX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) mod_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) case SKL_TKN_U32_ASTATE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (astate_table != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) dev_err(dev, "More than one entry for A-State count");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) if (tkn_elem->value > SKL_MAX_ASTATE_CFG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) dev_err(dev, "Invalid A-State count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) size = struct_size(skl->cfg.astate_cfg, astate_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) skl->cfg.astate_cfg = devm_kzalloc(dev, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) if (!skl->cfg.astate_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) astate_table = skl->cfg.astate_cfg->astate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) count = skl->cfg.astate_cfg->count = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) case SKL_TKN_U32_ASTATE_IDX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) if (tkn_elem->value >= count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) dev_err(dev, "Invalid A-State index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) tkn_elem->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) astate_cfg_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) case SKL_TKN_U32_ASTATE_KCPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) astate_table[astate_cfg_idx].kcps = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) case SKL_TKN_U32_ASTATE_CLK_SRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) astate_table[astate_cfg_idx].clk_src = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) case SKL_TKN_U8_IN_PIN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) case SKL_TKN_U8_OUT_PIN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) case SKL_TKN_U8_IN_QUEUE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) case SKL_TKN_U8_OUT_QUEUE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) case SKL_TKN_MM_U8_NUM_RES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) case SKL_TKN_MM_U8_NUM_INTF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) ret = skl_tplg_fill_mod_info(dev, tkn_elem, mod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) case SKL_TKN_U32_DIR_PIN_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) pin_idx = (tkn_elem->value & SKL_PIN_COUNT_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) case SKL_TKN_MM_U32_RES_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) res->id = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) res_val_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) case SKL_TKN_MM_U32_FMT_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) fmt->fmt_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) intf_val_idx = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) case SKL_TKN_MM_U32_CPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) case SKL_TKN_MM_U32_DMA_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) case SKL_TKN_MM_U32_CPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) case SKL_TKN_U32_MEM_PAGES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) case SKL_TKN_U32_OBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) case SKL_TKN_U32_IBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) case SKL_TKN_MM_U32_RES_PIN_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) case SKL_TKN_MM_U32_PIN_BUF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) ret = skl_tplg_fill_res_tkn(dev, tkn_elem, res, pin_idx, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) case SKL_TKN_MM_U32_NUM_IN_FMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) res->nr_input_pins = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) case SKL_TKN_MM_U32_NUM_OUT_FMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) res->nr_output_pins = tkn_elem->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) case SKL_TKN_U32_FMT_CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) case SKL_TKN_U32_FMT_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) case SKL_TKN_U32_FMT_BIT_DEPTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) case SKL_TKN_U32_FMT_SAMPLE_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) case SKL_TKN_U32_FMT_CH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) case SKL_TKN_U32_FMT_INTERLEAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) case SKL_TKN_U32_FMT_SAMPLE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) case SKL_TKN_U32_FMT_CH_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) case SKL_TKN_MM_U32_INTF_PIN_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) ret = skl_tplg_manifest_fill_fmt(dev, fmt, tkn_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) dir, pin_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) dev_err(dev, "Not a manifest token %d\n", tkn_elem->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) tkn_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) return tkn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) * Fill the manifest structure by parsing the tokens based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) static int skl_tplg_get_manifest_tkn(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) char *pvt_data, struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) int block_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) int tkn_count = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) int off = 0, tuple_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) u8 uuid_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) struct snd_soc_tplg_vendor_array *array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) struct snd_soc_tplg_vendor_value_elem *tkn_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) if (block_size <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) while (tuple_size < block_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) switch (array->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) case SND_SOC_TPLG_TUPLE_TYPE_STRING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) ret = skl_tplg_get_str_tkn(dev, array, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) tkn_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) tuple_size += tkn_count *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) sizeof(struct snd_soc_tplg_vendor_string_elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) case SND_SOC_TPLG_TUPLE_TYPE_UUID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) if (array->uuid->token != SKL_TKN_UUID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) dev_err(dev, "Not an UUID token: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) array->uuid->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) if (uuid_index >= skl->nr_modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) dev_err(dev, "Too many UUID tokens\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) import_guid(&skl->modules[uuid_index++]->uuid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) array->uuid->uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) tuple_size += sizeof(*array->uuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) tkn_elem = array->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) tkn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) while (tkn_count <= array->num_elems - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) ret = skl_tplg_get_int_tkn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) tkn_elem, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) tkn_count = tkn_count + ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) tkn_elem++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) tuple_size += (tkn_count * sizeof(*tkn_elem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) tkn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) * Parse manifest private data for tokens. The private data block is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) * preceded by descriptors for type and size of data block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) struct snd_soc_tplg_vendor_array *array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) int num_blocks, block_size = 0, block_type, off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) /* Read the NUM_DATA_BLOCKS descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) ret = skl_tplg_get_desc_blocks(dev, array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) num_blocks = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) while (num_blocks > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) array = (struct snd_soc_tplg_vendor_array *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) (manifest->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) ret = skl_tplg_get_desc_blocks(dev, array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) block_type = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) array = (struct snd_soc_tplg_vendor_array *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) (manifest->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) ret = skl_tplg_get_desc_blocks(dev, array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) block_size = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) off += array->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) array = (struct snd_soc_tplg_vendor_array *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) (manifest->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) data = (manifest->priv.data + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) if (block_type == SKL_TYPE_TUPLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) ret = skl_tplg_get_manifest_tkn(dev, data, skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) --num_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) off += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) static int skl_manifest_load(struct snd_soc_component *cmpnt, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) struct snd_soc_tplg_manifest *manifest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) struct hdac_bus *bus = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) /* proceed only if we have private data defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) if (manifest->priv.size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) skl_tplg_get_manifest_data(manifest, bus->dev, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) if (skl->lib_count > SKL_MAX_LIB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) skl->lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) static void skl_tplg_complete(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) struct snd_soc_dobj *dobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) struct snd_soc_acpi_mach *mach =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) dev_get_platdata(component->card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) list_for_each_entry(dobj, &component->dobj_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) struct snd_kcontrol *kcontrol = dobj->control.kcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) struct soc_enum *se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) char **texts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) char chan_text[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) if (dobj->type != SND_SOC_DOBJ_ENUM || !kcontrol ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) kcontrol->put != skl_tplg_multi_config_set_dmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) se = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) texts = dobj->control.dtexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) sprintf(chan_text, "c%d", mach->mach_params.dmic_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) for (i = 0; i < se->items; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) struct snd_ctl_elem_value val = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) if (strstr(texts[i], chan_text)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) val.value.enumerated.item[0] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) kcontrol->put(kcontrol, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) static struct snd_soc_tplg_ops skl_tplg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) .widget_load = skl_tplg_widget_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) .control_load = skl_tplg_control_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) .bytes_ext_ops = skl_tlv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) .io_ops = skl_tplg_kcontrol_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) .io_ops_count = ARRAY_SIZE(skl_tplg_kcontrol_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) .manifest = skl_manifest_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) .dai_load = skl_dai_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) .complete = skl_tplg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) * A pipe can have multiple modules, each of them will be a DAPM widget as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) * well. While managing a pipeline we need to get the list of all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) * helps to get the SKL type widgets in that pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) static int skl_tplg_create_pipe_widget_list(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) struct skl_module_cfg *mcfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) struct skl_pipe_module *p_module = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) struct skl_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) list_for_each_entry(w, &component->card->widgets, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) if (is_skl_dsp_widget_type(w, component->dev) && w->priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) mcfg = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) pipe = mcfg->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) p_module = devm_kzalloc(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) sizeof(*p_module), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (!p_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) p_module->w = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) list_add_tail(&p_module->node, &pipe->w_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) static void skl_tplg_set_pipe_type(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) struct skl_pipe_module *w_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) bool host_found = false, link_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) list_for_each_entry(w_module, &pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) w = w_module->w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) host_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) else if (mconfig->dev_type != SKL_DEVICE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) link_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) if (host_found && link_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) pipe->passthru = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) pipe->passthru = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) * SKL topology init routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) int skl_tplg_init(struct snd_soc_component *component, struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) struct skl_pipeline *ppl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) ret = request_firmware(&fw, skl->tplg_name, bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) char alt_tplg_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) snprintf(alt_tplg_name, sizeof(alt_tplg_name), "%s-tplg.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) skl->mach->drv_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) dev_info(bus->dev, "tplg fw %s load failed with %d, trying alternative tplg name %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) skl->tplg_name, ret, alt_tplg_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) ret = request_firmware(&fw, alt_tplg_name, bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) goto component_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) dev_info(bus->dev, "tplg %s failed with %d, falling back to dfw_sst.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) alt_tplg_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) "dfw_sst.bin", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) component_load:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) * The complete tplg for SKL is loaded as index 0, we don't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) * any other index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) ret = snd_soc_tplg_component_load(component, &skl_tplg_ops, fw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) dev_err(bus->dev, "tplg component load failed%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) ret = skl_tplg_create_pipe_widget_list(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) dev_err(bus->dev, "tplg create pipe widget list failed%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) list_for_each_entry(ppl, &skl->ppl_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) skl_tplg_set_pipe_type(skl, ppl->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) void skl_tplg_exit(struct snd_soc_component *component, struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) struct skl_pipeline *ppl, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) list_for_each_entry_safe(ppl, tmp, &skl->ppl_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) list_del(&ppl->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) /* clean up topology */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) snd_soc_tplg_component_remove(component, SND_SOC_TPLG_INDEX_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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