^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-sst.c - HDA DSP library functions for SKL platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-15, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../common/sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SKL_BASEFW_TIMEOUT 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SKL_INIT_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Intel HD Audio SRAM Window 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SKL_ADSP_SRAM0_BASE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Firmware status window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SKL_NUM_MODULES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 cur_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return (cur_sts == status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int skl_transfer_firmware(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const void *basefw, u32 base_fw_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SKL_ADSP_FW_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SKL_FW_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SKL_FW_RFW_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SKL_BASEFW_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "Firmware boot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ctx->cl_dev.ops.cl_stop_dma(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SKL_ADSP_FW_BIN_HDR_OFFSET 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int skl_load_base_firmware(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct firmware stripped_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) skl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) init_waitqueue_head(&skl->boot_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ctx->fw == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_err(ctx->dev, "Request firmware failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* prase uuids on first boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (skl->is_first_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = snd_skl_parse_uuids(ctx, ctx->fw, SKL_ADSP_FW_BIN_HDR_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_err(ctx->dev, "UUID parsing err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) release_firmware(ctx->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* check for extended manifest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) stripped_fw.data = ctx->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) stripped_fw.size = ctx->fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) skl_dsp_strip_extended_manifest(&stripped_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = skl_dsp_boot(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto skl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = skl_cldma_prepare(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(ctx->dev, "CL dma prepare failed : %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) goto skl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* enable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) skl_ipc_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) skl_ipc_op_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* check ROM Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (i = SKL_INIT_TIMEOUT; i > 0; --i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (skl_check_fw_status(ctx, SKL_FW_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_dbg(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "ROM loaded, we can continue with FW loading\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "Timeout waiting for ROM init done, reg:0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto transfer_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = skl_transfer_firmware(ctx, stripped_fw.data, stripped_fw.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto transfer_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto transfer_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) skl->fw_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) transfer_firmware_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ctx->cl_dev.ops.cl_cleanup_controller(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) skl_load_base_firmware_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) release_firmware(ctx->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ctx->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int skl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct skl_ipc_dxstate_info dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* If core0 is being turned on, we need to load the FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = skl_load_base_firmware(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(ctx->dev, "unable to load firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* load libs as they are also lost on D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (skl->lib_count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = ctx->fw_ops.load_library(ctx, skl->lib_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) skl->lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(ctx->dev, "reload libs failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * If any core other than core 0 is being moved to D0, enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * core and send the set dx IPC for the core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (core_id != SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = skl_dsp_enable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dx.core_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dx.dx_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SKL_BASE_FW_MODULE_ID, &dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(ctx->dev, "Failed to set dsp to D0:core id= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) skl_dsp_disable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) skl->cores.state[core_id] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int skl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct skl_ipc_dxstate_info dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dx.core_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dx.dx_mask = SKL_IPC_D3_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(ctx->dev, "set Dx core %d fail: %d\n", core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* disable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ctx->cl_dev.ops.cl_cleanup_controller(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) skl_cldma_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) skl_ipc_op_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) skl_ipc_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = skl_dsp_disable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) skl->cores.state[core_id] = SKL_DSP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static unsigned int skl_get_errorcode(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * since get/set_module are called from DAPM context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * we don't need lock for usage count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int skl_get_module(struct sst_dsp *ctx, u16 mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct skl_module_table *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) list_for_each_entry(module, &ctx->module_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (module->mod_info->mod_id == mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ++module->usage_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int skl_put_module(struct sst_dsp *ctx, u16 mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct skl_module_table *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) list_for_each_entry(module, &ctx->module_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (module->mod_info->mod_id == mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return --module->usage_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct skl_module_table *skl_fill_module_table(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) char *mod_name, int mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct skl_module_table *skl_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = request_firmware(&fw, mod_name, ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(ctx->dev, "Request Module %s failed :%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mod_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) skl_module = devm_kzalloc(ctx->dev, sizeof(*skl_module), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (skl_module == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) size = sizeof(*skl_module->mod_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) skl_module->mod_info = devm_kzalloc(ctx->dev, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (skl_module->mod_info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) skl_module->mod_info->mod_id = mod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) skl_module->mod_info->fw = fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) list_add(&skl_module->list, &ctx->module_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return skl_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* get a module from it's unique ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct skl_module_table *skl_module_get_from_id(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct sst_dsp *ctx, u16 mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct skl_module_table *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (list_empty(&ctx->module_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(ctx->dev, "Module list is empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) list_for_each_entry(module, &ctx->module_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (module->mod_info->mod_id == mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int skl_transfer_module(struct sst_dsp *ctx, const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 size, u16 mod_id, u8 table_id, bool is_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret, bytes_left, curr_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) skl->mod_load_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bytes_left = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, data, size, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (bytes_left < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* check is_module flag to load module or library */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (is_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = skl_ipc_load_modules(&skl->ipc, SKL_NUM_MODULES, &mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = skl_sst_ipc_load_library(&skl->ipc, 0, table_id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(ctx->dev, "Failed to Load %s with err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) is_module ? "module" : "lib", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * if bytes_left > 0 then wait for BDL complete interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * copy the next chunk till bytes_left is 0. if bytes_left is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * zero, then wait for load module IPC reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) while (bytes_left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) curr_pos = size - bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = skl_cldma_wait_interruptible(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bytes_left = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) data + curr_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bytes_left, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = wait_event_timeout(skl->mod_load_wait, skl->mod_load_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret == 0 || !skl->mod_load_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(ctx->dev, "Module Load failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctx->cl_dev.ops.cl_stop_dma(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) skl_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct firmware stripped_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* library indices start from 1 to N. 0 represents base FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (i = 1; i < lib_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) SKL_ADSP_FW_BIN_HDR_OFFSET, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto load_library_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = skl_transfer_module(ctx, stripped_fw.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) stripped_fw.size, 0, i, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto load_library_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) load_library_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) skl_release_library(linfo, lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int skl_load_module(struct sst_dsp *ctx, u16 mod_id, u8 *guid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct skl_module_table *module_entry = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) char mod_name[64]; /* guid str = 32 chars + 4 hyphens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) snprintf(mod_name, sizeof(mod_name), "intel/dsp_fw_%pUL.bin", guid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) module_entry = skl_module_get_from_id(ctx, mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (module_entry == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) module_entry = skl_fill_module_table(ctx, mod_name, mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (module_entry == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(ctx->dev, "Failed to Load module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!module_entry->usage_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = skl_transfer_module(ctx, module_entry->mod_info->fw->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) module_entry->mod_info->fw->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mod_id, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(ctx->dev, "Failed to Load module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = skl_get_module(ctx, mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int skl_unload_module(struct sst_dsp *ctx, u16 mod_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int usage_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) usage_cnt = skl_put_module(ctx, mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (usage_cnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(ctx->dev, "Module bad usage cnt!:%d\n", usage_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* if module is used by others return, no need to unload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (usage_cnt > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = skl_ipc_unload_modules(&skl->ipc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SKL_NUM_MODULES, &mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(ctx->dev, "Failed to UnLoad module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) skl_get_module(ctx, mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void skl_clear_module_cnt(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct skl_module_table *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (list_empty(&ctx->module_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) list_for_each_entry(module, &ctx->module_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) module->usage_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXPORT_SYMBOL_GPL(skl_clear_module_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void skl_clear_module_table(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct skl_module_table *module, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (list_empty(&ctx->module_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) list_for_each_entry_safe(module, tmp, &ctx->module_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) list_del(&module->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) release_firmware(module->mod_info->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct skl_dsp_fw_ops skl_fw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .set_state_D0 = skl_set_dsp_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .set_state_D3 = skl_set_dsp_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .load_fw = skl_load_base_firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .get_fw_errcode = skl_get_errorcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .load_library = skl_load_library,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .load_mod = skl_load_module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .unload_mod = skl_unload_module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct sst_ops skl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .irq_handler = skl_dsp_sst_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .write = sst_shim32_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .read = sst_shim32_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .free = skl_dsp_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct sst_dsp_device skl_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .thread = skl_dsp_irq_thread_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .ops = &skl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct skl_dev **dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct skl_dev *skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct sst_dsp *sst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(dev, "%s: no device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) skl = *dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) sst = skl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) sst->addr.lpe = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sst->addr.shim = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sst->addr.sram0_base = SKL_ADSP_SRAM0_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) sst->addr.sram1_base = SKL_ADSP_SRAM1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = skl_ipc_init(dev, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) skl_dsp_free(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) sst->fw_ops = skl_fw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return skl_dsp_acquire_irq(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) EXPORT_SYMBOL_GPL(skl_sst_dsp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int skl_sst_init_fw(struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct sst_dsp *sst = skl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = sst->fw_ops.load_fw(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(dev, "Load base fw failed : %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) skl_dsp_init_core_state(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (skl->lib_count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = sst->fw_ops.load_library(sst, skl->lib_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) skl->lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(dev, "Load Library failed : %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) skl->is_first_boot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) EXPORT_SYMBOL_GPL(skl_sst_init_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (skl->dsp->fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) release_firmware(skl->dsp->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) skl_clear_module_table(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) skl_freeup_uuid_list(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) skl_ipc_free(&skl->ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) skl->dsp->ops->free(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (skl->boot_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) skl->dsp->cl_dev.ops.cl_cleanup_controller(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) skl_cldma_int_disable(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DESCRIPTION("Intel Skylake IPC driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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