^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Skylake SST DSP Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-15, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __SKL_SST_DSP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __SKL_SST_DSP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/uuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/memalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "skl-sst-cldma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct sst_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct sst_dsp_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct skl_lib_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct skl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Intel HD Audio General DSP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SKL_ADSP_GEN_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Intel HD Audio Inter-Processor Communication Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SKL_ADSP_IPC_BASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* HIPCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SKL_ADSP_REG_HIPCI_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* HIPCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SKL_ADSP_REG_HIPCIE_DONE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* HIPCCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* HIPCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SKL_ADSP_REG_HIPCT_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* FW base IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SKL_INSTANCE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SKL_BASE_FW_MODULE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Intel HD Audio SRAM Window 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SKL_ADSP_SRAM1_BASE 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SKL_ADSP_MMIO_LEN 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SKL_ADSP_W0_STAT_SZ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SKL_ADSP_W0_UP_SZ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SKL_ADSP_W1_SZ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SKL_FW_STS_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SKL_FW_INIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SKL_FW_RFW_START 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BXT_FW_ROM_INIT_RETRY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BXT_INIT_TIMEOUT 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SKL_ADSPIC_IPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SKL_ADSPIS_IPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Core ID of core0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SKL_DSP_CORE0_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Mask for a given core index, c = 0.. number of supported cores - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SKL_DSP_CORE_MASK(c) BIT(c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * since Core0 is primary core and it is used often
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SKL_DSP_CORE0_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Mask for a given number of cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * nc = number of supported cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* ADSPCS - Audio DSP Control & Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Core Reset - asserted high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * CRST Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SKL_ADSPCS_CRST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Core run/stall - when set to '1' core is stalled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * CSTALL Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SKL_ADSPCS_CSTALL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Set Power Active - when set to '1' turn cores on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * SPA Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SKL_ADSPCS_SPA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Current Power Active - power status of cores, set by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * CPA Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SKL_ADSPCS_CPA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* DSP Core state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum skl_dsp_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SKL_DSP_RUNNING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Running in D0i3 state; can be in streaming or non-streaming D0i3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SKL_DSP_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* D0i3 substates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum skl_dsp_d0i3_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SKL_DSP_D0I3_NONE = -1, /* No D0i3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SKL_DSP_D0I3_NON_STREAMING = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SKL_DSP_D0I3_STREAMING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct skl_dsp_fw_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*load_fw)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* FW module parser/loader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int (*load_library)(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct skl_lib_info *linfo, int lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int (*parse_fw)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int (*set_state_D0i3)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int (*set_state_D0i0)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct skl_dsp_loader_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int (*alloc_dma_buf)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct snd_dma_buffer *dmab, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int (*free_dma_buf)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct snd_dma_buffer *dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int (*prepare)(struct device *dev, unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int byte_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct snd_dma_buffer *bufp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int (*trigger)(struct device *dev, bool start, int stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MAX_INSTANCE_BUFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct uuid_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) guid_t uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int is_loadable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int max_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u64 pvt_id[MAX_INSTANCE_BUFF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int *instance_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct skl_load_module_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u16 mod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct skl_module_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct skl_load_module_info *mod_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int usage_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void skl_cldma_process_intr(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void skl_cldma_int_disable(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int skl_cldma_prepare(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int skl_cldma_wait_interruptible(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sst_dsp_device *sst_dev, int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int skl_dsp_acquire_irq(struct sst_dsp *sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bool is_skl_dsp_running(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void skl_dsp_init_core_state(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int skl_dsp_wake(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int skl_dsp_sleep(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void skl_dsp_free(struct sst_dsp *dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int skl_dsp_boot(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct skl_dev **dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct skl_dev **dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int skl_sst_init_fw(struct device *dev, struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int offset, int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int skl_get_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int instance_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int skl_put_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int *pvt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int skl_get_pvt_instance_id_map(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int module_id, int instance_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void skl_freeup_uuid_list(struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int skl_dsp_strip_extended_manifest(struct firmware *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct sst_dsp_device *skl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int skl_prepare_lib_load(struct skl_dev *skl, struct skl_lib_info *linfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct firmware *stripped_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int hdr_offset, int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void skl_release_library(struct skl_lib_info *linfo, int lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #endif /*__SKL_SST_DSP_H__*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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