^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-sst-dsp.c - SKL SST library generic function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-15, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "../common/sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* various timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SKL_DSP_PU_TO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SKL_DSP_PD_TO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SKL_DSP_RESET_TO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) mutex_lock(&ctx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ctx->sst_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) mutex_unlock(&ctx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Initialize core power state and usage count. To be called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * successful first boot. Hence core 0 will be running and other cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * will be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void skl_dsp_init_core_state(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) skl->cores.usage_count[SKL_DSP_CORE0_ID] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (i = SKL_DSP_CORE0_ID + 1; i < skl->cores.count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) skl->cores.state[i] = SKL_DSP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) skl->cores.usage_count[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Get the mask for all enabled cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int core_mask, en_cores_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) core_mask = SKL_DSP_CORES_MASK(skl->cores.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Cores having CPA bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) en_cores_mask = (val & SKL_ADSPCS_CPA_MASK(core_mask)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SKL_ADSPCS_CPA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* And cores having CRST bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) en_cores_mask &= (~val & SKL_ADSPCS_CRST_MASK(core_mask)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SKL_ADSPCS_CRST_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* And cores having CSTALL bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) en_cores_mask &= (~val & SKL_ADSPCS_CSTALL_MASK(core_mask)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SKL_ADSPCS_CSTALL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) en_cores_mask &= core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_dbg(ctx->dev, "DSP enabled cores mask = %x\n", en_cores_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return en_cores_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) skl_dsp_core_set_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) sst_dsp_shim_update_bits_unlocked(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CRST_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SKL_ADSPCS_CRST_MASK(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SKL_ADSPCS_CRST_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SKL_ADSPCS_CRST_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SKL_DSP_RESET_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "Set reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SKL_ADSPCS_CRST_MASK(core_mask)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SKL_ADSPCS_CRST_MASK(core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(ctx->dev, "Set reset state failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int skl_dsp_core_unset_reset_state(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_dbg(ctx->dev, "In %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SKL_ADSPCS_CRST_MASK(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SKL_ADSPCS_CRST_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SKL_DSP_RESET_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "Unset reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SKL_ADSPCS_CRST_MASK(core_mask)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(ctx->dev, "Unset reset state failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) is_skl_dsp_core_enable(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool is_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) is_enable = ((val & SKL_ADSPCS_CPA_MASK(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (val & SKL_ADSPCS_SPA_MASK(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) !(val & SKL_ADSPCS_CRST_MASK(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) !(val & SKL_ADSPCS_CSTALL_MASK(core_mask)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_dbg(ctx->dev, "DSP core(s) enabled? %d : core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) is_enable, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return is_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int skl_dsp_reset_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* stall core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SKL_ADSPCS_CSTALL_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SKL_ADSPCS_CSTALL_MASK(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* set reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return skl_dsp_core_set_reset_state(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* unset reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = skl_dsp_core_unset_reset_state(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* run core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_dbg(ctx->dev, "unstall/run core: core_mask = %x\n", core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SKL_ADSPCS_CSTALL_MASK(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!is_skl_dsp_core_enable(ctx, core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) skl_dsp_reset_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(ctx->dev, "DSP start core failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SKL_ADSPCS_SPA_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SKL_ADSPCS_SPA_MASK(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SKL_ADSPCS_CPA_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SKL_ADSPCS_CPA_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SKL_DSP_PU_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "Power up");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SKL_ADSPCS_CPA_MASK(core_mask)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SKL_ADSPCS_CPA_MASK(core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(ctx->dev, "DSP core power up failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SKL_ADSPCS_SPA_MASK(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SKL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SKL_ADSPCS_CPA_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SKL_DSP_PD_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "Power down");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = skl_dsp_core_power_up(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(ctx->dev, "dsp core power up failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return skl_dsp_start_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = skl_dsp_reset_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(ctx->dev, "dsp core reset failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* power down core*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = skl_dsp_core_power_down(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(ctx->dev, "dsp core power down fail mask %x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) core_mask, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (is_skl_dsp_core_enable(ctx, core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(ctx->dev, "dsp core disable fail mask %x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) core_mask, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int skl_dsp_boot(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (is_skl_dsp_core_enable(ctx, SKL_DSP_CORE0_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = skl_dsp_reset_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(ctx->dev, "dsp core0 reset fail: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(ctx->dev, "dsp core0 start fail: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(ctx->dev, "dsp core0 disable fail: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = skl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct sst_dsp *ctx = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) irqreturn_t result = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock(&ctx->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ctx->intr_status = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (val == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_unlock(&ctx->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (val & SKL_ADSPIS_IPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) skl_ipc_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) result = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (val & SKL_ADSPIS_CL_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) skl_cldma_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) result = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_unlock(&ctx->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * skl_dsp_get_core/skl_dsp_put_core will be called inside DAPM context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * within the dapm mutex. Hence no separate lock is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (core_id >= skl->cores.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(ctx->dev, "invalid core id: %d\n", core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) skl->cores.usage_count[core_id]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (skl->cores.state[core_id] == SKL_DSP_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = ctx->fw_ops.set_state_D0(ctx, core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(ctx->dev, "unable to get core%d\n", core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_dbg(ctx->dev, "core id %d state %d usage_count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) core_id, skl->cores.state[core_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) skl->cores.usage_count[core_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) EXPORT_SYMBOL_GPL(skl_dsp_get_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (core_id >= skl->cores.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(ctx->dev, "invalid core id: %d\n", core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if ((--skl->cores.usage_count[core_id] == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (skl->cores.state[core_id] != SKL_DSP_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = ctx->fw_ops.set_state_D3(ctx, core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_err(ctx->dev, "unable to put core %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) skl->cores.usage_count[core_id]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_dbg(ctx->dev, "core id %d state %d usage_count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) core_id, skl->cores.state[core_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) skl->cores.usage_count[core_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) EXPORT_SYMBOL_GPL(skl_dsp_put_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int skl_dsp_wake(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return skl_dsp_get_core(ctx, SKL_DSP_CORE0_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) EXPORT_SYMBOL_GPL(skl_dsp_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int skl_dsp_sleep(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return skl_dsp_put_core(ctx, SKL_DSP_CORE0_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EXPORT_SYMBOL_GPL(skl_dsp_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct sst_dsp_device *sst_dev, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct sst_dsp *sst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sst = devm_kzalloc(dev, sizeof(*sst), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (sst == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spin_lock_init(&sst->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mutex_init(&sst->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) sst->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sst->sst_dev = sst_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sst->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) sst->ops = sst_dev->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sst->thread_context = sst_dev->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Initialise SST Audio DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (sst->ops->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = sst->ops->init(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return sst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int skl_dsp_acquire_irq(struct sst_dsp *sst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct sst_dsp_device *sst_dev = sst->sst_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Register the ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = request_threaded_irq(sst->irq, sst->ops->irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sst_dev->thread, IRQF_SHARED, "AudioDSP", sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(sst->dev, "unable to grab threaded IRQ %d, disabling device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sst->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) void skl_dsp_free(struct sst_dsp *dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) skl_ipc_int_disable(dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) free_irq(dsp->irq, dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) skl_ipc_op_int_disable(dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) skl_dsp_disable_core(dsp, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) EXPORT_SYMBOL_GPL(skl_dsp_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bool is_skl_dsp_running(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return (ctx->sst_state == SKL_DSP_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) EXPORT_SYMBOL_GPL(is_skl_dsp_running);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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