^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Code Loader DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef SKL_SST_CLDMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SKL_SST_CLDMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FW_CL_STREAM_NUMBER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DMA_ADDRESS_128_BITS_ALIGNMENT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BDL_ALIGN(x) (x >> DMA_ADDRESS_128_BITS_ALIGNMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SKL_ADSPIC_CL_DMA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SKL_ADSPIS_CL_DMA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SKL_CL_DMA_SD_INT_DESC_ERR 0x10 /* Descriptor error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SKL_CL_DMA_SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SKL_CL_DMA_SD_INT_COMPLETE 0x04 /* Buffer completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Intel HD Audio Code Loader DMA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HDA_ADSP_LOADER_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Stream Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SKL_ADSP_REG_CL_SD_CTL (HDA_ADSP_LOADER_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SKL_ADSP_REG_CL_SD_STS (HDA_ADSP_LOADER_BASE + 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SKL_ADSP_REG_CL_SD_LPIB (HDA_ADSP_LOADER_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SKL_ADSP_REG_CL_SD_CBL (HDA_ADSP_LOADER_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SKL_ADSP_REG_CL_SD_LVI (HDA_ADSP_LOADER_BASE + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SKL_ADSP_REG_CL_SD_FIFOW (HDA_ADSP_LOADER_BASE + 0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SKL_ADSP_REG_CL_SD_FIFOSIZE (HDA_ADSP_LOADER_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SKL_ADSP_REG_CL_SD_FORMAT (HDA_ADSP_LOADER_BASE + 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SKL_ADSP_REG_CL_SD_FIFOL (HDA_ADSP_LOADER_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SKL_ADSP_REG_CL_SD_BDLPL (HDA_ADSP_LOADER_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SKL_ADSP_REG_CL_SD_BDLPU (HDA_ADSP_LOADER_BASE + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* CL: Software Position Based FIFO Capability Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SKL_ADSP_REG_CL_SPBFIFO (HDA_ADSP_LOADER_BASE + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCH (SKL_ADSP_REG_CL_SPBFIFO + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL (SKL_ADSP_REG_CL_SPBFIFO + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SKL_ADSP_REG_CL_SPBFIFO_SPIB (SKL_ADSP_REG_CL_SPBFIFO + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SKL_ADSP_REG_CL_SPBFIFO_MAXFIFOS (SKL_ADSP_REG_CL_SPBFIFO + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* CL: Stream Descriptor x Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Stream Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CL_SD_CTL_SRST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CL_SD_CTL_SRST_MASK (1 << CL_SD_CTL_SRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CL_SD_CTL_SRST(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Stream Run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CL_SD_CTL_RUN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CL_SD_CTL_RUN_MASK (1 << CL_SD_CTL_RUN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CL_SD_CTL_RUN(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Interrupt On Completion Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CL_SD_CTL_IOCE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CL_SD_CTL_IOCE_MASK (1 << CL_SD_CTL_IOCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CL_SD_CTL_IOCE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* FIFO Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CL_SD_CTL_FEIE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CL_SD_CTL_FEIE_MASK (1 << CL_SD_CTL_FEIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CL_SD_CTL_FEIE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Descriptor Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CL_SD_CTL_DEIE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CL_SD_CTL_DEIE_MASK (1 << CL_SD_CTL_DEIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CL_SD_CTL_DEIE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((x << CL_SD_CTL_DEIE_SHIFT) & CL_SD_CTL_DEIE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* FIFO Limit Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CL_SD_CTL_FIFOLC_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CL_SD_CTL_FIFOLC_MASK (1 << CL_SD_CTL_FIFOLC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CL_SD_CTL_FIFOLC(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ((x << CL_SD_CTL_FIFOLC_SHIFT) & CL_SD_CTL_FIFOLC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Stripe Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CL_SD_CTL_STRIPE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CL_SD_CTL_STRIPE_MASK (0x3 << CL_SD_CTL_STRIPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CL_SD_CTL_STRIPE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ((x << CL_SD_CTL_STRIPE_SHIFT) & CL_SD_CTL_STRIPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Traffic Priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CL_SD_CTL_TP_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CL_SD_CTL_TP_MASK (1 << CL_SD_CTL_TP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CL_SD_CTL_TP(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ((x << CL_SD_CTL_TP_SHIFT) & CL_SD_CTL_TP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Bidirectional Direction Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CL_SD_CTL_DIR_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CL_SD_CTL_DIR_MASK (1 << CL_SD_CTL_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CL_SD_CTL_DIR(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ((x << CL_SD_CTL_DIR_SHIFT) & CL_SD_CTL_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Stream Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CL_SD_CTL_STRM_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CL_SD_CTL_STRM_MASK (0xf << CL_SD_CTL_STRM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CL_SD_CTL_STRM(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ((x << CL_SD_CTL_STRM_SHIFT) & CL_SD_CTL_STRM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* CL: Stream Descriptor x Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Buffer Completion Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CL_SD_STS_BCIS(x) CL_SD_CTL_IOCE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* FIFO Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CL_SD_STS_FIFOE(x) CL_SD_CTL_FEIE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Descriptor Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CL_SD_STS_DESE(x) CL_SD_CTL_DEIE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* FIFO Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CL_SD_STS_FIFORDY(x) CL_SD_CTL_FIFOLC(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* CL: Stream Descriptor x Last Valid Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CL_SD_LVI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CL_SD_LVI_MASK (0xff << CL_SD_LVI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CL_SD_LVI(x) ((x << CL_SD_LVI_SHIFT) & CL_SD_LVI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* CL: Stream Descriptor x FIFO Eviction Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CL_SD_FIFOW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CL_SD_FIFOW_MASK (0x7 << CL_SD_FIFOW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CL_SD_FIFOW(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ((x << CL_SD_FIFOW_SHIFT) & CL_SD_FIFOW_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Protect Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CL_SD_BDLPLBA_PROT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CL_SD_BDLPLBA_PROT_MASK (1 << CL_SD_BDLPLBA_PROT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CL_SD_BDLPLBA_PROT(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ((x << CL_SD_BDLPLBA_PROT_SHIFT) & CL_SD_BDLPLBA_PROT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Buffer Descriptor List Lower Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CL_SD_BDLPLBA_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CL_SD_BDLPLBA_MASK (0x1ffffff << CL_SD_BDLPLBA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CL_SD_BDLPLBA(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ((BDL_ALIGN(lower_32_bits(x)) << CL_SD_BDLPLBA_SHIFT) & CL_SD_BDLPLBA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Buffer Descriptor List Upper Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CL_SD_BDLPUBA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CL_SD_BDLPUBA_MASK (0xffffffff << CL_SD_BDLPUBA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CL_SD_BDLPUBA(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ((upper_32_bits(x) << CL_SD_BDLPUBA_SHIFT) & CL_SD_BDLPUBA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Code Loader - Software Position Based FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Capability Registers x Software Position Based FIFO Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Next Capability Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CL_SPBFIFO_SPBFCH_PTR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CL_SPBFIFO_SPBFCH_PTR_MASK (0xff << CL_SPBFIFO_SPBFCH_PTR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CL_SPBFIFO_SPBFCH_PTR(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ((x << CL_SPBFIFO_SPBFCH_PTR_SHIFT) & CL_SPBFIFO_SPBFCH_PTR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Capability Identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CL_SPBFIFO_SPBFCH_ID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CL_SPBFIFO_SPBFCH_ID_MASK (0xfff << CL_SPBFIFO_SPBFCH_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CL_SPBFIFO_SPBFCH_ID(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ((x << CL_SPBFIFO_SPBFCH_ID_SHIFT) & CL_SPBFIFO_SPBFCH_ID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Capability Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CL_SPBFIFO_SPBFCH_VER_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CL_SPBFIFO_SPBFCH_VER_MASK (0xf << CL_SPBFIFO_SPBFCH_VER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CL_SPBFIFO_SPBFCH_VER(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ((x << CL_SPBFIFO_SPBFCH_VER_SHIFT) & CL_SPBFIFO_SPBFCH_VER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Software Position in Buffer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CL_SPBFIFO_SPBFCCTL_SPIBE_MASK (1 << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CL_SPBFIFO_SPBFCCTL_SPIBE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ((x << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* SST IPC SKL defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SKL_WAIT_TIMEOUT 500 /* 500 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SKL_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum skl_cl_dma_wake_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SKL_CL_DMA_STATUS_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SKL_CL_DMA_BUF_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SKL_CL_DMA_ERR, /* TODO: Expand the error states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct sst_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct skl_cl_dev_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void (*cl_setup_bdle)(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct snd_dma_buffer *dmab_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __le32 **bdlp, int size, int with_ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void (*cl_setup_controller)(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct snd_dma_buffer *dmab_bdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int max_size, u32 page_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void (*cl_setup_spb)(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int size, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void (*cl_cleanup_spb)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void (*cl_trigger)(struct sst_dsp *ctx, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void (*cl_cleanup_controller)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int (*cl_copy_to_dmabuf)(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const void *bin, u32 size, bool wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void (*cl_stop_dma)(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * skl_cl_dev - holds information for code loader dma transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @dmab_data: buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @dmab_bdl: buffer descriptor list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @bufsize: ring buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @frags: Last valid buffer descriptor index in the BDL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @curr_spib_pos: Current position in ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @dma_buffer_offset: dma buffer offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @ops: operations supported on CL dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @wait_queue: wait queue to wake for wake event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @wake_status: DMA wake status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @wait_condition: condition to wait on wait queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @cl_dma_lock: for synchronized access to cldma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct skl_cl_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct snd_dma_buffer dmab_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct snd_dma_buffer dmab_bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int curr_spib_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int dma_buffer_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct skl_cl_dev_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) wait_queue_head_t wait_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int wake_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bool wait_condition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #endif /* SKL_SST_CLDMA_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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