^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-ssp-clk.h - Skylake ssp clock information and ipc structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef SOUND_SOC_SKL_SSP_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SOUND_SOC_SKL_SSP_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SKL_MAX_SSP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* xtal/cardinal/pll, parent of ssp clocks and mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SKL_MAX_CLK_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SKL_MAX_SSP_CLK_TYPES 3 /* mclk, sclk, sclkfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SKL_MAX_CLK_CNT (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Max number of configurations supported for each clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SKL_MAX_CLK_RATES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SKL_SCLK_OFS SKL_MAX_SSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SKL_SCLKFS_OFS (SKL_SCLK_OFS + SKL_MAX_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum skl_clk_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SKL_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SKL_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SKL_SCLK_FS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum skl_clk_src_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SKL_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SKL_CARDINAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SKL_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct skl_clk_parent_src {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct skl_tlv_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct skl_dmactrl_mclk_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct skl_tlv_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* DMA Clk TLV params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 clk_warm_up:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 mclk:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 warm_up_over:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 rsvd0:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 clk_stop_delay:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 keep_running:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 clk_stop_over:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 rsvd1:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct skl_dmactrl_sclkfs_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct skl_tlv_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* DMA SClk&FS TLV params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 sampling_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 channel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 channel_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 interleaving_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 number_of_channels : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 valid_bit_depth : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 sample_type : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 reserved : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) union skl_clk_ctrl_ipc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct skl_dmactrl_mclk_cfg mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct skl_dmactrl_sclkfs_cfg sclk_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct skl_clk_rate_cfg_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) union skl_clk_ctrl_ipc dma_ctl_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * all possible clocks ssp can generate for that platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct skl_ssp_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct skl_clk_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct skl_clk_parent_src *parent_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct skl_ssp_clk *ssp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void *pvt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* SOUND_SOC_SKL_SSP_CLK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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