^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright(c) 2015-17 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * skl-ssp-clk.c - ASoC skylake ssp clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/intel-nhlt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "skl-ssp-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "skl-topology.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define to_skl_clk(_hw) container_of(_hw, struct skl_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct skl_clk_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_lookup *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct skl_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_lookup *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct skl_clk_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct skl_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct skl_clk_parent parent[SKL_MAX_CLK_SRC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct skl_clk *clk[SKL_MAX_CLK_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 avail_clk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int skl_get_clk_type(u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case 0 ... (SKL_SCLK_OFS - 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return SKL_MCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case SKL_SCLK_OFS ... (SKL_SCLKFS_OFS - 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return SKL_SCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case SKL_SCLKFS_OFS ... (SKL_MAX_CLK_CNT - 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return SKL_SCLK_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int skl_get_vbus_id(u32 index, u8 clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (clk_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case SKL_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case SKL_SCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return index - SKL_SCLK_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case SKL_SCLK_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return index - SKL_SCLKFS_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void skl_fill_clk_ipc(struct skl_clk_rate_cfg_table *rcfg, u8 clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct nhlt_fmt_cfg *fmt_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) union skl_clk_ctrl_ipc *ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct wav_fmt *wfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!rcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ipc = &rcfg->dma_ctl_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (clk_type == SKL_SCLK_FS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) fmt_cfg = (struct nhlt_fmt_cfg *)rcfg->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) wfmt = &fmt_cfg->fmt_ext.fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Remove TLV Header size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ipc->sclk_fs.hdr.size = sizeof(struct skl_dmactrl_sclkfs_cfg) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sizeof(struct skl_tlv_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ipc->sclk_fs.sampling_frequency = wfmt->samples_per_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ipc->sclk_fs.bit_depth = wfmt->bits_per_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ipc->sclk_fs.valid_bit_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) fmt_cfg->fmt_ext.sample.valid_bits_per_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ipc->sclk_fs.number_of_channels = wfmt->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ipc->mclk.hdr.type = DMA_CLK_CONTROLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Remove TLV Header size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ipc->mclk.hdr.size = sizeof(struct skl_dmactrl_mclk_cfg) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sizeof(struct skl_tlv_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Sends dma control IPC to turn the clock ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int skl_send_clk_dma_control(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct skl_clk_rate_cfg_table *rcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 vbus_id, u8 clk_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct nhlt_specific_cfg *sp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 i2s_config_size, node_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct nhlt_fmt_cfg *fmt_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) union skl_clk_ctrl_ipc *ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void *i2s_config = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 *data, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!rcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ipc = &rcfg->dma_ctl_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) fmt_cfg = (struct nhlt_fmt_cfg *)rcfg->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sp_cfg = &fmt_cfg->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (clk_type == SKL_SCLK_FS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ipc->sclk_fs.hdr.type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enable ? DMA_TRANSMITION_START : DMA_TRANSMITION_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data = (u8 *)&ipc->sclk_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) size = sizeof(struct skl_dmactrl_sclkfs_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* 1 to enable mclk, 0 to enable sclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (clk_type == SKL_SCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ipc->mclk.mclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ipc->mclk.mclk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ipc->mclk.keep_running = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ipc->mclk.warm_up_over = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ipc->mclk.clk_stop_over = !enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) data = (u8 *)&ipc->mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) size = sizeof(struct skl_dmactrl_mclk_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) i2s_config_size = sp_cfg->size + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) i2s_config = kzalloc(i2s_config_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!i2s_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* copy blob */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) memcpy(i2s_config, sp_cfg->caps, sp_cfg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* copy additional dma controls information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) memcpy(i2s_config + sp_cfg->size, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) node_id = ((SKL_DMA_I2S_LINK_INPUT_CLASS << 8) | (vbus_id << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = skl_dsp_set_dma_control(skl, (u32 *)i2s_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) i2s_config_size, node_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) kfree(i2s_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct skl_clk_rate_cfg_table *skl_get_rate_cfg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct skl_clk_rate_cfg_table *rcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; (i < SKL_MAX_CLK_RATES) && rcfg[i].rate; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (rcfg[i].rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return &rcfg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int skl_clk_change_status(struct skl_clk *clkdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct skl_clk_rate_cfg_table *rcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int vbus_id, clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk_type = skl_get_clk_type(clkdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (clk_type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) vbus_id = skl_get_vbus_id(clkdev->id, clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (vbus_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return vbus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rcfg = skl_get_rate_cfg(clkdev->pdata->ssp_clks[clkdev->id].rate_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clkdev->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!rcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return skl_send_clk_dma_control(clkdev->pdata->pvt_data, rcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) vbus_id, clk_type, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int skl_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct skl_clk *clkdev = to_skl_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return skl_clk_change_status(clkdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void skl_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct skl_clk *clkdev = to_skl_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) skl_clk_change_status(clkdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int skl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct skl_clk *clkdev = to_skl_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct skl_clk_rate_cfg_table *rcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rcfg = skl_get_rate_cfg(clkdev->pdata->ssp_clks[clkdev->id].rate_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!rcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) clk_type = skl_get_clk_type(clkdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (clk_type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) skl_fill_clk_ipc(rcfg, clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) clkdev->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static unsigned long skl_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct skl_clk *clkdev = to_skl_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (clkdev->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return clkdev->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Not supported by clk driver. Implemented to satisfy clk fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static long skl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * prepare/unprepare are used instead of enable/disable as IPC will be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * in non-atomic context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct clk_ops skl_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .prepare = skl_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .unprepare = skl_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .set_rate = skl_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .round_rate = skl_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .recalc_rate = skl_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void unregister_parent_src_clk(struct skl_clk_parent *pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) while (id--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clkdev_drop(pclk[id].lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk_hw_unregister_fixed_rate(pclk[id].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void unregister_src_clk(struct skl_clk_data *dclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (dclk->avail_clk_cnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clkdev_drop(dclk->clk[dclk->avail_clk_cnt]->lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int skl_register_parent_clks(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct skl_clk_parent *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct skl_clk_parent_src *pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 0; i < SKL_MAX_CLK_SRC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Register Parent clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) parent[i].hw = clk_hw_register_fixed_rate(dev, pclk[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pclk[i].parent_name, 0, pclk[i].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (IS_ERR(parent[i].hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = PTR_ERR(parent[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) parent[i].lookup = clkdev_hw_create(parent[i].hw, pclk[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!parent[i].lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_hw_unregister_fixed_rate(parent[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unregister_parent_src_clk(parent, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Assign fmt_config to clk_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct skl_clk *register_skl_clk(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct skl_ssp_clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct skl_clk_pdata *clk_pdata, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct skl_clk *clkdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clkdev = devm_kzalloc(dev, sizeof(*clkdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!clkdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) init.name = clk->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) init.ops = &skl_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) init.flags = CLK_SET_RATE_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) init.parent_names = &clk->parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clkdev->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) clkdev->pdata = clk_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clkdev->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = devm_clk_hw_register(dev, &clkdev->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clkdev = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return clkdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clkdev->lookup = clkdev_hw_create(&clkdev->hw, init.name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!clkdev->lookup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clkdev = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return clkdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int skl_clk_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct device *parent_dev = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct skl_clk_parent_src *parent_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct skl_clk_pdata *clk_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct skl_clk_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct skl_ssp_clk *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk_pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) parent_clks = clk_pdata->parent_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) clks = clk_pdata->ssp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!parent_clks || !clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Register Parent clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = skl_register_parent_clks(parent_dev, data->parent, parent_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < clk_pdata->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Only register valid clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * i.e. for which nhlt entry is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (clks[i].rate_cfg[0].rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) data->clk[data->avail_clk_cnt] = register_skl_clk(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) &clks[i], clk_pdata, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (IS_ERR(data->clk[data->avail_clk_cnt])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = PTR_ERR(data->clk[data->avail_clk_cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto err_unreg_skl_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data->avail_clk_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err_unreg_skl_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unregister_src_clk(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unregister_parent_src_clk(data->parent, SKL_MAX_CLK_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int skl_clk_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct skl_clk_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unregister_src_clk(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unregister_parent_src_clk(data->parent, SKL_MAX_CLK_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct platform_driver skl_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "skl-ssp-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .probe = skl_clk_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .remove = skl_clk_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) module_platform_driver(skl_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_DESCRIPTION("Skylake clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_AUTHOR("Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_ALIAS("platform:skl-ssp-clk");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags