^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2015 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "skl-topology.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "skl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "skl-sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HDA_MONO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HDA_STEREO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HDA_QUAD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HDA_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct snd_pcm_hardware azx_pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SNDRV_PCM_INFO_SYNC_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SNDRV_PCM_INFO_HAS_LINK_ATIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SNDRV_PCM_RATE_8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .buffer_bytes_max = AZX_MAX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .period_bytes_min = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .periods_max = AZX_MAX_FRAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct hdac_stream *hstream = hdac_stream(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct hdac_bus *bus = hstream->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int skl_substream_alloc_pages(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) hdac_stream(stream)->bufsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hdac_stream(stream)->period_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) hdac_stream(stream)->format_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void skl_set_pcm_constrains(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* avoid wrap-around with wall-clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 20, 178000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (bus->ppcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return HDAC_EXT_STREAM_TYPE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return HDAC_EXT_STREAM_TYPE_COUPLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * check if the stream opened is marked as ignore_suspend by machine, if so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * then enable suspend_active refcount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * The count supend_active does not need lock as it is used in open/close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * and suspend context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void skl_set_suspend_active(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct snd_soc_dai *dai, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) w = snd_soc_dai_get_widget(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (w->ignore_suspend && enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) skl->supend_active++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else if (w->ignore_suspend && !enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) skl->supend_active--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int format_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct hdac_stream *hstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) hstream = snd_hdac_get_stream(bus, params->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) params->host_dma_id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!hstream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) stream = stream_to_hdac_ext_stream(hstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) snd_hdac_ext_stream_decouple(bus, stream, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) format_val = snd_hdac_calc_stream_format(params->s_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) params->ch, params->format, params->host_bps, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) format_val, params->s_freq, params->ch, params->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) snd_hdac_stream_reset(hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * The recommended SDxFMT programming sequence for BXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * platforms is to couple the stream before writing the format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_BXT(skl->pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) snd_hdac_ext_stream_decouple(bus, stream, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = snd_hdac_stream_setup(hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) snd_hdac_ext_stream_decouple(bus, stream, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) err = snd_hdac_stream_setup(hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) hdac_stream(stream)->prepared = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int format_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct hdac_stream *hstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct hdac_ext_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned char stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) hstream = snd_hdac_get_stream(bus, params->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) params->link_dma_id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!hstream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) stream = stream_to_hdac_ext_stream(hstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) snd_hdac_ext_stream_decouple(bus, stream, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) params->format, params->link_bps, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) format_val, params->s_freq, params->ch, params->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) snd_hdac_ext_link_stream_reset(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) snd_hdac_ext_link_stream_setup(stream, format_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) stream_tag = hstream->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) list_for_each_entry(link, &bus->hlink_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (link->index == params->link_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) snd_hdac_ext_link_set_stream_id(link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) stream->link_prepared = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int skl_pcm_open(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct skl_dma_params *dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct skl_dev *skl = get_skl_ctx(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) stream = snd_hdac_ext_stream_assign(bus, substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) skl_get_host_stream_type(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (stream == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) skl_set_pcm_constrains(bus, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * disable WALLCLOCK timestamps for capture streams
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * until we figure out how to handle digital inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) runtime->private_data = stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!dma_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dma_params->stream_tag = hdac_stream(stream)->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snd_soc_dai_set_dma_data(dai, substream, dma_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dma_params->stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) skl_set_suspend_active(substream, dai, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int skl_pcm_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct skl_dev *skl = get_skl_ctx(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * In case of XRUN recovery or in the case when the application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * calls prepare another time, reset the FW pipe to clean state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (mconfig &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mconfig->pipe->state == SKL_PIPE_CREATED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mconfig->pipe->state == SKL_PIPE_PAUSED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = skl_reset_pipe(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = skl_pcm_host_dma_prepare(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mconfig->pipe->p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct skl_pipe_params p_params = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct skl_module_cfg *m_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret, dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = skl_substream_alloc_pages(bus, substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) params_buffer_bytes(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) runtime->rate, runtime->channels, runtime->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dma_id = hdac_stream(stream)->stream_tag - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) p_params.s_fmt = snd_pcm_format_width(params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) p_params.ch = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) p_params.s_freq = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) p_params.host_dma_id = dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) p_params.stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) p_params.format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) p_params.host_bps = dai->driver->playback.sig_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) p_params.host_bps = dai->driver->capture.sig_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (m_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void skl_pcm_close(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct skl_dma_params *dma_params = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dma_params = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * now we should set this to NULL as we are freeing by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * dma_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) snd_soc_dai_set_dma_data(dai, substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) skl_set_suspend_active(substream, dai, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * check if close is for "Reference Pin" and set back the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * CGCTL.MISCBDCGE if disabled by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!strncmp(dai->name, "Reference Pin", 13) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) skl->miscbdcg_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) skl->enable_miscbdcge(dai->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) skl->miscbdcg_disabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) kfree(dma_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct skl_dev *skl = get_skl_ctx(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (mconfig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = skl_reset_pipe(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(dai->dev, "%s:Reset failed ret =%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) snd_hdac_stream_cleanup(hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hdac_stream(stream)->prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int skl_be_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct skl_pipe_params p_params = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) p_params.s_fmt = snd_pcm_format_width(params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) p_params.ch = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) p_params.s_freq = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) p_params.stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return skl_tplg_be_update_params(dai, &p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct hdac_bus *bus = get_bus_ctx(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct hdac_stream *hstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hstr = hdac_stream(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!hstr->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) start = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_lock_irqsave(&bus->reg_lock, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) snd_hdac_stream_start(hdac_stream(stream), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) snd_hdac_stream_timecounter_init(hstr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) snd_hdac_stream_stop(hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_unlock_irqrestore(&bus->reg_lock, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct skl_dev *skl = get_skl_ctx(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct hdac_bus *bus = get_bus_ctx(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) w = snd_soc_dai_get_widget(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!w->ignore_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * enable DMA Resume enable bit for the stream, set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * dpib & lpib position to resume before starting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) snd_hdac_ext_stream_drsm_enable(bus, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hdac_stream(stream)->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_hdac_ext_stream_set_dpibr(bus, stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) stream->lpib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Start HOST DMA and Start FE Pipe.This is to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * there are no underrun/overrun in the case when the FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * pipeline is started but there is a delay in starting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * DMA channel on the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = skl_decoupled_trigger(substream, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return skl_run_pipe(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Stop FE Pipe first and stop DMA. This is to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * there are no underrun/overrun in the case if there is a delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * between the two operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = skl_stop_pipe(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = skl_decoupled_trigger(substream, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* save the dpib and lpib positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) stream->dpib = readl(bus->remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) AZX_REG_VS_SDXDPIB_XBASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (AZX_REG_VS_SDXDPIB_XINTERVAL *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hdac_stream(stream)->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) stream->lpib = snd_hdac_stream_get_pos_lpib(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) snd_hdac_ext_stream_decouple(bus, stream, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int skl_link_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct hdac_ext_stream *link_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct skl_pipe_params p_params = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct hdac_ext_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) link_dev = snd_hdac_ext_stream_assign(bus, substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) HDAC_EXT_STREAM_TYPE_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!link_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) stream_tag = hdac_stream(link_dev)->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* set the stream tag in the codec dai dma params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) p_params.s_fmt = snd_pcm_format_width(params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) p_params.ch = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) p_params.s_freq = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) p_params.stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) p_params.link_dma_id = stream_tag - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) p_params.link_index = link->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) p_params.format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) p_params.link_bps = codec_dai->driver->playback.sig_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) p_params.link_bps = codec_dai->driver->capture.sig_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return skl_tplg_be_update_params(dai, &p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct skl_dev *skl = get_skl_ctx(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct skl_module_cfg *mconfig = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* In case of XRUN recovery, reset the FW pipe to clean state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (mconfig && !mconfig->pipe->passthru &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) skl_reset_pipe(skl, mconfig->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct hdac_ext_stream *link_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct hdac_bus *bus = get_bus_ctx(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) snd_hdac_ext_link_stream_start(link_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) snd_hdac_ext_link_stream_clear(link_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) snd_hdac_ext_stream_decouple(bus, stream, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int skl_link_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct hdac_ext_stream *link_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct hdac_ext_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned char stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) link_dev->link_prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) link = snd_hdac_ext_bus_get_link(bus, asoc_rtd_to_codec(rtd, 0)->component->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) stream_tag = hdac_stream(link_dev)->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) snd_hdac_ext_link_clear_stream_id(link, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .startup = skl_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .shutdown = skl_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .prepare = skl_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .hw_params = skl_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .hw_free = skl_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .trigger = skl_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .hw_params = skl_be_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .hw_params = skl_be_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const struct snd_soc_dai_ops skl_link_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .prepare = skl_link_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .hw_params = skl_link_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .hw_free = skl_link_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .trigger = skl_link_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct snd_soc_dai_driver skl_fe_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .name = "System Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .stream_name = "System Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .stream_name = "System Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "System Pin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .stream_name = "Headset Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) SNDRV_PCM_RATE_8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .name = "Echoref Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .stream_name = "Echoreference Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SNDRV_PCM_RATE_8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .name = "Reference Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .stream_name = "Reference Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .channels_max = HDA_QUAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .name = "Deepbuffer Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .stream_name = "Deepbuffer Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "LowLatency Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .stream_name = "Low Latency Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .name = "DMIC Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .stream_name = "DMIC Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .channels_max = HDA_QUAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .name = "HDMI1 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .stream_name = "HDMI1 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .name = "HDMI2 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .stream_name = "HDMI2 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .name = "HDMI3 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .ops = &skl_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .stream_name = "HDMI3 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .sig_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* BE CPU Dais */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static struct snd_soc_dai_driver skl_platform_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "SSP0 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .ops = &skl_be_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .stream_name = "ssp0 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .stream_name = "ssp0 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .name = "SSP1 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .ops = &skl_be_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .stream_name = "ssp1 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .stream_name = "ssp1 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "SSP2 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .ops = &skl_be_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .stream_name = "ssp2 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .stream_name = "ssp2 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .name = "SSP3 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .ops = &skl_be_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .stream_name = "ssp3 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .stream_name = "ssp3 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .name = "SSP4 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .ops = &skl_be_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .stream_name = "ssp4 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .stream_name = "ssp4 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = "SSP5 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .ops = &skl_be_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .stream_name = "ssp5 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .stream_name = "ssp5 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .channels_max = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .name = "iDisp1 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .ops = &skl_link_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .stream_name = "iDisp1 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .name = "iDisp2 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .ops = &skl_link_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .stream_name = "iDisp2 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .name = "iDisp3 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .ops = &skl_link_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .stream_name = "iDisp3 Tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .channels_min = HDA_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .name = "DMIC01 Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .ops = &skl_dmic_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .stream_name = "DMIC01 Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .channels_max = HDA_QUAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .name = "DMIC16k Pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .ops = &skl_dmic_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .stream_name = "DMIC16k Rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .channels_max = HDA_QUAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .rates = SNDRV_PCM_RATE_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .name = "Analog CPU DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .ops = &skl_link_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .stream_name = "Analog CPU Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .channels_max = HDA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .stream_name = "Analog CPU Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .channels_max = HDA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .name = "Alt Analog CPU DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .ops = &skl_link_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .stream_name = "Alt Analog CPU Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .channels_max = HDA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .stream_name = "Alt Analog CPU Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .channels_max = HDA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .name = "Digital CPU DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ops = &skl_link_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .stream_name = "Digital CPU Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .channels_max = HDA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .stream_name = "Digital CPU Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .channels_min = HDA_MONO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .channels_max = HDA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int skl_dai_load(struct snd_soc_component *cmp, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct snd_soc_dai_driver *dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dai_drv->ops = &skl_pcm_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int skl_platform_soc_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct snd_soc_dai_link *dai_link = rtd->dai_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dai_link->cpus->dai_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int skl_coupled_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct hdac_bus *bus = get_bus_ctx(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) bool start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int sbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) unsigned long cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct hdac_stream *hstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) stream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) hstr = hdac_stream(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!hstr->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) start = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) start = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (s->pcm->card != substream->pcm->card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) stream = get_hdac_ext_stream(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) sbits |= 1 << hdac_stream(stream)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) spin_lock_irqsave(&bus->reg_lock, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* first, set SYNC bits of corresponding streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (s->pcm->card != substream->pcm->card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) stream = get_hdac_ext_stream(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) snd_hdac_stream_start(hdac_stream(stream), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) snd_hdac_stream_stop(hdac_stream(stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) spin_unlock_irqrestore(&bus->reg_lock, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) snd_hdac_stream_sync(hstr, start, sbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) spin_lock_irqsave(&bus->reg_lock, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* reset SYNC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) snd_hdac_stream_timecounter_init(hstr, sbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) spin_unlock_irqrestore(&bus->reg_lock, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int skl_platform_soc_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct hdac_bus *bus = get_bus_ctx(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (!bus->ppcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return skl_coupled_trigger(substream, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static snd_pcm_uframes_t skl_platform_soc_pointer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct hdac_bus *bus = get_bus_ctx(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) unsigned int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Use DPIB for Playback stream as the periodic DMA Position-in-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * Buffer Writes may be scheduled at the same time or later than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * the MSI and does not guarantee to reflect the Position of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * last buffer that was transferred. Whereas DPIB register in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * HAD space reflects the actual data that is transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * Use the position buffer for capture, as DPIB write gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * completed earlier than the actual data written to the DDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * For capture stream following workaround is required to fix the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * incorrect position reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * 1. Wait for 20us before reading the DMA position in buffer once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * the interrupt is generated for stream completion as update happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * on the HDA frame boundary i.e. 20.833uSec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * 2. Read DPIB register to flush the DMA position value. This dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * read is required to flush DMA position value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * 3. Read the DMA Position-in-Buffer. This value now will be equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * or greater than period boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) (AZX_REG_VS_SDXDPIB_XINTERVAL *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) hdac_stream(hstream)->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) readl(bus->remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) AZX_REG_VS_SDXDPIB_XBASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) (AZX_REG_VS_SDXDPIB_XINTERVAL *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) hdac_stream(hstream)->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (pos >= hdac_stream(hstream)->bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return bytes_to_frames(substream->runtime, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int skl_platform_soc_mmap(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct vm_area_struct *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return snd_pcm_lib_default_mmap(substream, area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u64 nsec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u64 codec_frames, codec_nsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!codec_dai->driver->ops->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) codec_nsecs = div_u64(codec_frames * 1000000000LL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return nsec + codec_nsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static int skl_platform_soc_get_time_info(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct timespec64 *system_ts, struct timespec64 *audio_ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct hdac_stream *hstr = hdac_stream(sstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) u64 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) snd_pcm_gettime(substream->runtime, system_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) nsec = timecounter_read(&hstr->tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) nsec = div_u64(nsec, 3); /* can be optimized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (audio_tstamp_config->report_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) nsec = skl_adjust_codec_delay(substream, nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) *audio_ts = ns_to_timespec64(nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int skl_platform_soc_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct hdac_bus *bus = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (dai->driver->playback.channels_min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dai->driver->capture.channels_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* buffer pre-allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (size > MAX_PREALLOC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) size = MAX_PREALLOC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) snd_pcm_set_managed_buffer_all(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) &skl->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) size, MAX_PREALLOC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int skl_get_module_info(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct skl_module_inst_id *pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) guid_t *uuid_mod, *uuid_tplg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct skl_module *skl_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct uuid_module *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) int i, ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) uuid_mod = (guid_t *)mconfig->guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (list_empty(&skl->uuid_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dev_err(skl->dev, "Module list is empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) for (i = 0; i < skl->nr_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) skl_module = skl->modules[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) uuid_tplg = &skl_module->uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (guid_equal(uuid_mod, uuid_tplg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mconfig->module = skl_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (skl->nr_modules && ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) list_for_each_entry(module, &skl->uuid_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (guid_equal(uuid_mod, &module->uuid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) mconfig->id.module_id = module->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) mconfig->module->loadable = module->is_loadable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) for (i = 0; i < MAX_IN_QUEUE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) pin_id = &mconfig->m_in_pin[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (guid_equal(&pin_id->mod_uuid, &module->uuid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pin_id->module_id = module->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) for (i = 0; i < MAX_OUT_QUEUE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) pin_id = &mconfig->m_out_pin[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (guid_equal(&pin_id->mod_uuid, &module->uuid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) pin_id->module_id = module->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static int skl_populate_modules(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct skl_pipeline *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct skl_pipe_module *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct snd_soc_dapm_widget *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct skl_module_cfg *mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) list_for_each_entry(p, &skl->ppl_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) list_for_each_entry(m, &p->pipe->w_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) w = m->w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mconfig = w->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = skl_get_module_info(skl, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(skl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) "query module info failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) skl_tplg_add_moduleid_in_bind_params(skl, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static int skl_platform_soc_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct hdac_bus *bus = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) const struct skl_dsp_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) pm_runtime_get_sync(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (bus->ppcap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) skl->component = component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* init debugfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) skl->debugfs = skl_debugfs_init(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = skl_tplg_init(component, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_err(component->dev, "Failed to init topology!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* load the firmwares, since all is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ops = skl_get_dsp_ops(skl->pci->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * Disable dynamic clock and power gating during firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * and library download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) skl->enable_miscbdcge(component->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) skl->clock_power_gating(component->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = ops->init_fw(component->dev, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) skl->enable_miscbdcge(component->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) skl->clock_power_gating(component->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) skl_populate_modules(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) skl->update_d0i3c = skl_update_d0i3c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (skl->cfg.astate_cfg != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) skl_dsp_set_astate_cfg(skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) skl->cfg.astate_cfg->count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) skl->cfg.astate_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) pm_runtime_mark_last_busy(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pm_runtime_put_autosuspend(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static void skl_platform_soc_remove(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct hdac_bus *bus = dev_get_drvdata(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) skl_tplg_exit(component, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) skl_debugfs_exit(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const struct snd_soc_component_driver skl_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .probe = skl_platform_soc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .remove = skl_platform_soc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .open = skl_platform_soc_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .trigger = skl_platform_soc_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .pointer = skl_platform_soc_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .get_time_info = skl_platform_soc_get_time_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .mmap = skl_platform_soc_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .pcm_construct = skl_platform_soc_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int skl_platform_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct snd_soc_dai_driver *dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) int num_dais = ARRAY_SIZE(skl_platform_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (!skl->dais) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (!skl->use_tplg_pcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) sizeof(skl_platform_dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (!dais) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) skl->dais = dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) sizeof(skl_fe_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) num_dais += ARRAY_SIZE(skl_fe_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ret = devm_snd_soc_register_component(dev, &skl_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) skl->dais, num_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_err(dev, "soc component registration failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) int skl_platform_unregister(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct skl_module_deferred_bind *modules, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) list_del(&modules->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) kfree(modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) kfree(skl->dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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