^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-message.c - HDA DSP interface for FW registration, Pipe and Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <uapi/sound/skl-tplg-interface.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "skl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "cnl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "skl-sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "skl-topology.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int skl_alloc_dma_buf(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct snd_dma_buffer *dmab, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev, size, dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) snd_dma_free_pages(dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SKL_ASTATE_PARAM_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct skl_ipc_large_config_msg msg = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) msg.large_param_id = SKL_ASTATE_PARAM_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) msg.param_data_size = (cnt * sizeof(struct skl_astate_param) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) sizeof(cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) skl_ipc_set_large_config(&skl->ipc, &msg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int skl_dsp_setup_spib(struct device *dev, unsigned int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int stream_tag, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct hdac_stream *stream = snd_hdac_get_stream(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct hdac_ext_stream *estream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) estream = stream_to_hdac_ext_stream(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* enable/disable SPIB for this hdac stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) snd_hdac_ext_stream_spbcap_enable(bus, enable, stream->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* set the spib value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) snd_hdac_ext_stream_set_spib(bus, estream, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int skl_dsp_prepare(struct device *dev, unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int size, struct snd_dma_buffer *dmab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct hdac_ext_stream *estream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct hdac_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct snd_pcm_substream substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) memset(&substream, 0, sizeof(substream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) substream.stream = SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) estream = snd_hdac_ext_stream_assign(bus, &substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) HDAC_EXT_STREAM_TYPE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!estream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) stream = hdac_stream(estream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* assign decouple host dma channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = snd_hdac_dsp_prepare(stream, format, size, dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) skl_dsp_setup_spib(dev, size, stream->stream_tag, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return stream->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int skl_dsp_trigger(struct device *dev, bool start, int stream_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct hdac_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) stream = snd_hdac_get_stream(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) snd_hdac_dsp_trigger(stream, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int skl_dsp_cleanup(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct snd_dma_buffer *dmab, int stream_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct hdac_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct hdac_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct hdac_ext_stream *estream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) stream = snd_hdac_get_stream(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) estream = stream_to_hdac_ext_stream(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) skl_dsp_setup_spib(dev, 0, stream_tag, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) snd_hdac_ext_stream_release(estream, HDAC_EXT_STREAM_TYPE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) snd_hdac_dsp_cleanup(stream, dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct skl_dsp_loader_ops skl_get_loader_ops(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct skl_dsp_loader_ops loader_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) memset(&loader_ops, 0, sizeof(struct skl_dsp_loader_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) loader_ops.free_dma_buf = skl_free_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return loader_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct skl_dsp_loader_ops bxt_get_loader_ops(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct skl_dsp_loader_ops loader_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) memset(&loader_ops, 0, sizeof(loader_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) loader_ops.free_dma_buf = skl_free_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) loader_ops.prepare = skl_dsp_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) loader_ops.trigger = skl_dsp_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) loader_ops.cleanup = skl_dsp_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return loader_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct skl_dsp_ops dsp_ops[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .id = 0x9d70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .num_cores = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .loader_ops = skl_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .init = skl_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .init_fw = skl_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .cleanup = skl_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .id = 0x9d71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .num_cores = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .loader_ops = skl_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .init = skl_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .init_fw = skl_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .cleanup = skl_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .id = 0x5a98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .num_cores = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .loader_ops = bxt_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .init = bxt_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .init_fw = bxt_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .cleanup = bxt_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .id = 0x3198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .num_cores = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .loader_ops = bxt_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .init = bxt_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .init_fw = bxt_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .cleanup = bxt_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .id = 0x9dc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .num_cores = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .loader_ops = bxt_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .init = cnl_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .init_fw = cnl_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .cleanup = cnl_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .id = 0xa348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .num_cores = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .loader_ops = bxt_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .init = cnl_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .init_fw = cnl_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cleanup = cnl_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .id = 0x02c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .num_cores = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .loader_ops = bxt_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .init = cnl_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .init_fw = cnl_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .cleanup = cnl_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .id = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .num_cores = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .loader_ops = bxt_get_loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .init = cnl_sst_dsp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .init_fw = cnl_sst_init_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .cleanup = cnl_sst_dsp_cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0; i < ARRAY_SIZE(dsp_ops); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (dsp_ops[i].id == pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return &dsp_ops[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int skl_init_dsp(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct skl_dsp_loader_ops loader_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int irq = bus->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const struct skl_dsp_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct skl_dsp_cores *cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* enable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) snd_hdac_ext_bus_ppcap_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) snd_hdac_ext_bus_ppcap_int_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* read the BAR of the ADSP MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mmio_base = pci_ioremap_bar(skl->pci, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (mmio_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(bus->dev, "ioremap error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ops = skl_get_dsp_ops(skl->pci->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto unmap_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) loader_ops = ops->loader_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = ops->init(bus->dev, mmio_base, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) skl->fw_name, loader_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) &skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto unmap_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) skl->dsp_ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cores = &skl->cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cores->count = ops->num_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cores->state = kcalloc(cores->count, sizeof(*cores->state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!cores->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) goto unmap_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cores->usage_count = kcalloc(cores->count, sizeof(*cores->usage_count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!cores->usage_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto free_core_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_dbg(bus->dev, "dsp registration status=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) free_core_state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) kfree(cores->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unmap_mmio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) iounmap(mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int skl_free_dsp(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* disable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) snd_hdac_ext_bus_ppcap_int_enable(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) skl->dsp_ops->cleanup(bus->dev, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) kfree(skl->cores.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) kfree(skl->cores.usage_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (skl->dsp->addr.lpe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) iounmap(skl->dsp->addr.lpe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * In the case of "suspend_active" i.e, the Audio IP being active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * during system suspend, immediately excecute any pending D0i3 work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * before suspending. This is needed for the IP to work in low power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * mode during system suspend. In the case of normal suspend, cancel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * any pending D0i3 work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int skl_suspend_late_dsp(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct delayed_work *dwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dwork = &skl->d0i3.work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (dwork->work.func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (skl->supend_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) flush_delayed_work(dwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cancel_delayed_work_sync(dwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int skl_suspend_dsp(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* if ppcap is not supported return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!bus->ppcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = skl_dsp_sleep(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* disable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) snd_hdac_ext_bus_ppcap_int_enable(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_hdac_ext_bus_ppcap_enable(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int skl_resume_dsp(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* if ppcap is not supported return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!bus->ppcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* enable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) snd_hdac_ext_bus_ppcap_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) snd_hdac_ext_bus_ppcap_int_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* check if DSP 1st boot is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (skl->is_first_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Disable dynamic clock and power gating during firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * and library download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) skl->enable_miscbdcge(skl->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) skl->clock_power_gating(skl->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = skl_dsp_wake(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) skl->enable_miscbdcge(skl->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) skl->clock_power_gating(skl->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (skl->cfg.astate_cfg != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) skl_dsp_set_astate_cfg(skl, skl->cfg.astate_cfg->count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) skl->cfg.astate_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) enum skl_bitdepth skl_get_bit_depth(int params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return SKL_DEPTH_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return SKL_DEPTH_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return SKL_DEPTH_24BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return SKL_DEPTH_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return SKL_DEPTH_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Each module in DSP expects a base module configuration, which consists of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * PCM format information, which we calculate in driver and resource values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * which are read from widget information passed through topology binary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * This is send when we create a module with INIT_INSTANCE IPC msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void skl_set_base_module_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct skl_base_cfg *base_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct skl_module *module = mconfig->module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct skl_module_res *res = &module->resources[mconfig->res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct skl_module_fmt *format = &fmt->inputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) base_cfg->audio_fmt.number_of_channels = format->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) base_cfg->audio_fmt.s_freq = format->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) base_cfg->audio_fmt.bit_depth = format->bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) base_cfg->audio_fmt.ch_cfg = format->ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) base_cfg->audio_fmt.sample_type = format->sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(skl->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) format->bit_depth, format->valid_bit_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) format->ch_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) base_cfg->audio_fmt.channel_map = format->ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) base_cfg->audio_fmt.interleaving = format->interleaving_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) base_cfg->cpc = res->cpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) base_cfg->ibs = res->ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) base_cfg->obs = res->obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) base_cfg->is_pages = res->is_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Copies copier capabilities into copier module and updates copier module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * config size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void skl_copy_copier_caps(struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct skl_cpr_cfg *cpr_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (mconfig->formats_config.caps_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) memcpy(cpr_mconfig->gtw_cfg.config_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mconfig->formats_config.caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mconfig->formats_config.caps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cpr_mconfig->gtw_cfg.config_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (mconfig->formats_config.caps_size) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * Calculate the gatewat settings required for copier module, type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * gateway and index of gateway to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static u32 skl_get_node_id(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) union skl_connector_node_id node_id = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) union skl_ssp_dma_node ssp_node = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct skl_pipe_params *params = mconfig->pipe->p_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) switch (mconfig->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case SKL_DEVICE_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) node_id.node.dma_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SKL_DMA_I2S_LINK_OUTPUT_CLASS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SKL_DMA_I2S_LINK_INPUT_CLASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) node_id.node.vindex = params->host_dma_id +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (mconfig->vbus_id << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case SKL_DEVICE_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) node_id.node.dma_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SKL_DMA_I2S_LINK_OUTPUT_CLASS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SKL_DMA_I2S_LINK_INPUT_CLASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ssp_node.dma_node.time_slot_index = mconfig->time_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ssp_node.dma_node.i2s_instance = mconfig->vbus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) node_id.node.vindex = ssp_node.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case SKL_DEVICE_DMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) node_id.node.vindex = mconfig->vbus_id +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) (mconfig->time_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case SKL_DEVICE_HDALINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) node_id.node.dma_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SKL_DMA_HDA_LINK_OUTPUT_CLASS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SKL_DMA_HDA_LINK_INPUT_CLASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) node_id.node.vindex = params->link_dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case SKL_DEVICE_HDAHOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) node_id.node.dma_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SKL_DMA_HDA_HOST_OUTPUT_CLASS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SKL_DMA_HDA_HOST_INPUT_CLASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) node_id.node.vindex = params->host_dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) node_id.val = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return node_id.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void skl_setup_cpr_gateway_cfg(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct skl_cpr_cfg *cpr_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 dma_io_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct skl_module_res *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int res_idx = mconfig->res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cpr_mconfig->gtw_cfg.node_id = skl_get_node_id(skl, mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (cpr_mconfig->gtw_cfg.node_id == SKL_NON_GATEWAY_CPR_NODE_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cpr_mconfig->cpr_feature_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (skl->nr_modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) res = &mconfig->module->resources[mconfig->res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) cpr_mconfig->gtw_cfg.dma_buffer_size = res->dma_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto skip_buf_size_calc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) res = &mconfig->module->resources[res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) switch (mconfig->hw_conn_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case SKL_CONN_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dma_io_buf = res->ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dma_io_buf = res->obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case SKL_CONN_SINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dma_io_buf = res->obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dma_io_buf = res->ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_warn(skl->dev, "wrong connection type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mconfig->hw_conn_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cpr_mconfig->gtw_cfg.dma_buffer_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mconfig->dma_buffer_size * dma_io_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* fallback to 2ms default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!cpr_mconfig->gtw_cfg.dma_buffer_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (mconfig->hw_conn_type == SKL_CONN_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * res->obs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * res->ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) skip_buf_size_calc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cpr_mconfig->cpr_feature_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cpr_mconfig->gtw_cfg.config_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) skl_copy_copier_caps(mconfig, cpr_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define DMA_CONTROL_ID 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define DMA_I2S_BLOB_SIZE 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 caps_size, u32 node_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct skl_dma_control *dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct skl_ipc_large_config_msg msg = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * if blob size zero, then return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (caps_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) msg.large_param_id = DMA_CONTROL_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) msg.param_data_size = sizeof(struct skl_dma_control) + caps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dma_ctrl = kzalloc(msg.param_data_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (dma_ctrl == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma_ctrl->node_id = node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * NHLT blob may contain additional configs along with i2s blob.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * firmware expects only the i2s blob size as the config_length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * So fix to i2s blob size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * size in dwords.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dma_ctrl->config_length = DMA_I2S_BLOB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) memcpy(dma_ctrl->config_data, caps, caps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) err = skl_ipc_set_large_config(&skl->ipc, &msg, (u32 *)dma_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) kfree(dma_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) EXPORT_SYMBOL_GPL(skl_dsp_set_dma_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static void skl_setup_out_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct skl_audio_data_format *out_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct skl_module *module = mconfig->module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct skl_module_fmt *format = &fmt->outputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) out_fmt->number_of_channels = (u8)format->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) out_fmt->s_freq = format->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) out_fmt->bit_depth = format->bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) out_fmt->valid_bit_depth = format->valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) out_fmt->ch_cfg = format->ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) out_fmt->channel_map = format->ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) out_fmt->interleaving = format->interleaving_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) out_fmt->sample_type = format->sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_dbg(skl->dev, "copier out format chan=%d fre=%d bitdepth=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) out_fmt->number_of_channels, format->s_freq, format->bit_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * DSP needs SRC module for frequency conversion, SRC takes base module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * configuration and the target frequency as extra parameter passed as src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void skl_set_src_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct skl_src_module_cfg *src_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct skl_module *module = mconfig->module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct skl_module_iface *iface = &module->formats[mconfig->fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct skl_module_fmt *fmt = &iface->outputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) skl_set_base_module_format(skl, mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) (struct skl_base_cfg *)src_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) src_mconfig->src_cfg = fmt->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * DSP needs updown module to do channel conversion. updown module take base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * module configuration and channel configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * It also take coefficients and now we have defaults applied here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void skl_set_updown_mixer_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct skl_up_down_mixer_cfg *mixer_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct skl_module *module = mconfig->module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct skl_module_iface *iface = &module->formats[mconfig->fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct skl_module_fmt *fmt = &iface->outputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) skl_set_base_module_format(skl, mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) (struct skl_base_cfg *)mixer_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mixer_mconfig->out_ch_cfg = fmt->ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mixer_mconfig->ch_map = fmt->ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * 'copier' is DSP internal module which copies data from Host DMA (HDA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * dma) or link (hda link, SSP, PDM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * Here we calculate the copier module parameters, like PCM format, output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * format, gateway settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void skl_set_copier_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct skl_cpr_cfg *cpr_mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) skl_set_base_module_format(skl, mconfig, base_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) skl_setup_out_format(skl, mconfig, out_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) skl_setup_cpr_gateway_cfg(skl, mconfig, cpr_mconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * Algo module are DSP pre processing modules. Algo module take base module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * configuration and params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static void skl_set_algo_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct skl_algo_cfg *algo_mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)algo_mcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) skl_set_base_module_format(skl, mconfig, base_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (mconfig->formats_config.caps_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) memcpy(algo_mcfg->params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mconfig->formats_config.caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mconfig->formats_config.caps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Mic select module allows selecting one or many input channels, thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * acting as a demux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Mic select module take base module configuration and out-format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void skl_set_base_outfmt_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct skl_module_cfg *mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct skl_base_outfmt_cfg *base_outfmt_mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct skl_audio_data_format *out_fmt = &base_outfmt_mcfg->out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct skl_base_cfg *base_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) (struct skl_base_cfg *)base_outfmt_mcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) skl_set_base_module_format(skl, mconfig, base_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) skl_setup_out_format(skl, mconfig, out_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static u16 skl_get_module_param_size(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u16 param_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) switch (mconfig->m_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case SKL_MODULE_TYPE_COPIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) param_size = sizeof(struct skl_cpr_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) param_size += mconfig->formats_config.caps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return param_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case SKL_MODULE_TYPE_SRCINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return sizeof(struct skl_src_module_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case SKL_MODULE_TYPE_UPDWMIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return sizeof(struct skl_up_down_mixer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case SKL_MODULE_TYPE_ALGO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) param_size = sizeof(struct skl_base_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) param_size += mconfig->formats_config.caps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return param_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case SKL_MODULE_TYPE_BASE_OUTFMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case SKL_MODULE_TYPE_MIC_SELECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return sizeof(struct skl_base_outfmt_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case SKL_MODULE_TYPE_MIXER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case SKL_MODULE_TYPE_KPB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return sizeof(struct skl_base_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * return only base cfg when no specific module type is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return sizeof(struct skl_base_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * DSP firmware supports various modules like copier, SRC, updown etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * These modules required various parameters to be calculated and sent for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * the module initialization to DSP. By default a generic module needs only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * base module format configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int skl_set_module_format(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct skl_module_cfg *module_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u16 *module_config_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) void **param_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u16 param_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) param_size = skl_get_module_param_size(skl, module_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) *param_data = kzalloc(param_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (NULL == *param_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *module_config_size = param_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) switch (module_config->m_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case SKL_MODULE_TYPE_COPIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) skl_set_copier_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case SKL_MODULE_TYPE_SRCINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) skl_set_src_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case SKL_MODULE_TYPE_UPDWMIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) skl_set_updown_mixer_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case SKL_MODULE_TYPE_ALGO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) skl_set_algo_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case SKL_MODULE_TYPE_BASE_OUTFMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case SKL_MODULE_TYPE_MIC_SELECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) skl_set_base_outfmt_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case SKL_MODULE_TYPE_MIXER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case SKL_MODULE_TYPE_KPB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) skl_set_base_module_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) skl_set_base_module_format(skl, module_config, *param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_dbg(skl->dev, "Module type=%d id=%d config size: %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) module_config->m_type, module_config->id.module_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) param_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) print_hex_dump_debug("Module params:", DUMP_PREFIX_OFFSET, 8, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) *param_data, param_size, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int skl_get_queue_index(struct skl_module_pin *mpin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct skl_module_inst_id id, int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) for (i = 0; i < max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (mpin[i].id.module_id == id.module_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mpin[i].id.instance_id == id.instance_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Allocates queue for each module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * if dynamic, the pin_index is allocated 0 to max_pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * In static, the pin_index is fixed based on module_id and instance id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static int skl_alloc_queue(struct skl_module_pin *mpin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct skl_module_cfg *tgt_cfg, int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct skl_module_inst_id id = tgt_cfg->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * if pin in dynamic, find first free pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * otherwise find match module and instance id pin as topology will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * ensure a unique pin is assigned to this so no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * allocate/free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) for (i = 0; i < max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (mpin[i].is_dynamic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!mpin[i].in_use &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) mpin[i].pin_state == SKL_PIN_UNBIND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) mpin[i].in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) mpin[i].id.module_id = id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mpin[i].id.instance_id = id.instance_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) mpin[i].id.pvt_id = id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mpin[i].tgt_mcfg = tgt_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (mpin[i].id.module_id == id.module_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mpin[i].id.instance_id == id.instance_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mpin[i].pin_state == SKL_PIN_UNBIND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) mpin[i].tgt_mcfg = tgt_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void skl_free_queue(struct skl_module_pin *mpin, int q_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (mpin[q_index].is_dynamic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mpin[q_index].in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mpin[q_index].id.module_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) mpin[q_index].id.instance_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mpin[q_index].id.pvt_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) mpin[q_index].pin_state = SKL_PIN_UNBIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mpin[q_index].tgt_mcfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Module state will be set to unint, if all the out pin state is UNBIND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void skl_clear_module_state(struct skl_module_pin *mpin, int max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) for (i = 0; i < max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (mpin[i].pin_state == SKL_PIN_UNBIND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mcfg->m_state = SKL_MODULE_INIT_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * A module needs to be instanataited in DSP. A mdoule is present in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * collection of module referred as a PIPE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * We first calculate the module format, based on module type and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int skl_init_module(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct skl_module_cfg *mconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u16 module_config_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) void *param_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct skl_ipc_init_instance_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev_dbg(skl->dev, "%s: module_id = %d instance=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mconfig->id.module_id, mconfig->id.pvt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (mconfig->pipe->state != SKL_PIPE_CREATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev_err(skl->dev, "Pipe not created state= %d pipe_id= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mconfig->pipe->state, mconfig->pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = skl_set_module_format(skl, mconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) &module_config_size, ¶m_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_err(skl->dev, "Failed to set module format ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) msg.module_id = mconfig->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) msg.instance_id = mconfig->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) msg.ppl_instance_id = mconfig->pipe->ppl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) msg.param_data_size = module_config_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) msg.core_id = mconfig->core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) msg.domain = mconfig->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = skl_ipc_init_instance(&skl->ipc, &msg, param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(skl->dev, "Failed to init instance ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) kfree(param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mconfig->m_state = SKL_MODULE_INIT_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) kfree(param_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void skl_dump_bind_info(struct skl_dev *skl, struct skl_module_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *src_module, struct skl_module_cfg *dst_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_dbg(skl->dev, "%s: src module_id = %d src_instance=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) __func__, src_module->id.module_id, src_module->id.pvt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_dbg(skl->dev, "%s: dst_module=%d dst_instance=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dst_module->id.module_id, dst_module->id.pvt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_dbg(skl->dev, "src_module state = %d dst module state = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) src_module->m_state, dst_module->m_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * On module freeup, we need to unbind the module with modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * it is already bind.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Find the pin allocated and unbind then using bind_unbind IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int skl_unbind_modules(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct skl_module_cfg *src_mcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct skl_module_cfg *dst_mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct skl_ipc_bind_unbind_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct skl_module_inst_id src_id = src_mcfg->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct skl_module_inst_id dst_id = dst_mcfg->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int in_max = dst_mcfg->module->max_input_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int out_max = src_mcfg->module->max_output_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int src_index, dst_index, src_pin_state, dst_pin_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) skl_dump_bind_info(skl, src_mcfg, dst_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* get src queue index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (src_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) msg.src_queue = src_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* get dst queue index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (dst_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) msg.dst_queue = dst_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) src_pin_state = src_mcfg->m_out_pin[src_index].pin_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dst_pin_state = dst_mcfg->m_in_pin[dst_index].pin_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (src_pin_state != SKL_PIN_BIND_DONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dst_pin_state != SKL_PIN_BIND_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) msg.module_id = src_mcfg->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) msg.instance_id = src_mcfg->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) msg.dst_module_id = dst_mcfg->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) msg.dst_instance_id = dst_mcfg->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) msg.bind = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = skl_ipc_bind_unbind(&skl->ipc, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* free queue only if unbind is success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) skl_free_queue(src_mcfg->m_out_pin, src_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) skl_free_queue(dst_mcfg->m_in_pin, dst_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * check only if src module bind state, bind is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * always from src -> sink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) skl_clear_module_state(src_mcfg->m_out_pin, out_max, src_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static void fill_pin_params(struct skl_audio_data_format *pin_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct skl_module_fmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pin_fmt->number_of_channels = format->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pin_fmt->s_freq = format->s_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pin_fmt->bit_depth = format->bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pin_fmt->valid_bit_depth = format->valid_bit_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pin_fmt->ch_cfg = format->ch_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pin_fmt->sample_type = format->sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) pin_fmt->channel_map = format->ch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pin_fmt->interleaving = format->interleaving_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define CPR_SINK_FMT_PARAM_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * Once a module is instantiated it need to be 'bind' with other modules in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * the pipeline. For binding we need to find the module pins which are bind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * This function finds the pins and then sends bund_unbind IPC message to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * DSP using IPC helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int skl_bind_modules(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct skl_module_cfg *src_mcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct skl_module_cfg *dst_mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct skl_ipc_bind_unbind_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int in_max = dst_mcfg->module->max_input_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int out_max = src_mcfg->module->max_output_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int src_index, dst_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct skl_module_fmt *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct skl_cpr_pin_fmt pin_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct skl_module *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct skl_module_iface *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) skl_dump_bind_info(skl, src_mcfg, dst_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (src_mcfg->m_state < SKL_MODULE_INIT_DONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dst_mcfg->m_state < SKL_MODULE_INIT_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_mcfg, out_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (src_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) msg.src_queue = src_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_mcfg, in_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (dst_index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) skl_free_queue(src_mcfg->m_out_pin, src_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * Copier module requires the separate large_config_set_ipc to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * configure the pins other than 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (src_mcfg->m_type == SKL_MODULE_TYPE_COPIER && src_index > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pin_fmt.sink_id = src_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) module = src_mcfg->module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) fmt = &module->formats[src_mcfg->fmt_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Input fmt is same as that of src module input cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) format = &fmt->inputs[0].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) fill_pin_params(&(pin_fmt.src_fmt), format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) format = &fmt->outputs[src_index].fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) fill_pin_params(&(pin_fmt.dst_fmt), format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = skl_set_module_params(skl, (void *)&pin_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) sizeof(struct skl_cpr_pin_fmt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) CPR_SINK_FMT_PARAM_ID, src_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) msg.dst_queue = dst_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) dev_dbg(skl->dev, "src queue = %d dst queue =%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) msg.src_queue, msg.dst_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) msg.module_id = src_mcfg->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) msg.instance_id = src_mcfg->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) msg.dst_module_id = dst_mcfg->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) msg.dst_instance_id = dst_mcfg->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) msg.bind = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = skl_ipc_bind_unbind(&skl->ipc, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) src_mcfg->m_state = SKL_MODULE_BIND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) src_mcfg->m_out_pin[src_index].pin_state = SKL_PIN_BIND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dst_mcfg->m_in_pin[dst_index].pin_state = SKL_PIN_BIND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* error case , if IPC fails, clear the queue index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) skl_free_queue(src_mcfg->m_out_pin, src_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) skl_free_queue(dst_mcfg->m_in_pin, dst_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int skl_set_pipe_state(struct skl_dev *skl, struct skl_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) enum skl_ipc_pipeline_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dev_dbg(skl->dev, "%s: pipe_state = %d\n", __func__, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return skl_ipc_set_pipeline_state(&skl->ipc, pipe->ppl_id, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * A pipeline is a collection of modules. Before a module in instantiated a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * pipeline needs to be created for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * This function creates pipeline, by sending create pipeline IPC messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * to FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dev_dbg(skl->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = skl_ipc_create_pipeline(&skl->ipc, pipe->memory_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pipe->pipe_priority, pipe->ppl_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pipe->lp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(skl->dev, "Failed to create pipeline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) pipe->state = SKL_PIPE_CREATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * A pipeline needs to be deleted on cleanup. If a pipeline is running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * then pause it first. Before actual deletion, pipeline should enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * reset state. Finish the procedure by sending delete pipeline IPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * DSP will stop the DMA engines and release resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dev_dbg(skl->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* If pipe was not created in FW, do not try to delete it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (pipe->state < SKL_PIPE_CREATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* If pipe is started, do stop the pipe in FW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (pipe->state >= SKL_PIPE_STARTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = skl_set_pipe_state(skl, pipe, PPL_PAUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_err(skl->dev, "Failed to stop pipeline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pipe->state = SKL_PIPE_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* reset pipe state before deletion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = skl_set_pipe_state(skl, pipe, PPL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(skl->dev, "Failed to reset pipe ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pipe->state = SKL_PIPE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = skl_ipc_delete_pipeline(&skl->ipc, pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_err(skl->dev, "Failed to delete pipeline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pipe->state = SKL_PIPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * A pipeline is also a scheduling entity in DSP which can be run, stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * For processing data the pipe need to be run by sending IPC set pipe state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * to DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev_dbg(skl->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* If pipe was not created in FW, do not try to pause or delete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (pipe->state < SKL_PIPE_CREATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* Pipe has to be paused before it is started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = skl_set_pipe_state(skl, pipe, PPL_PAUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_err(skl->dev, "Failed to pause pipe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pipe->state = SKL_PIPE_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = skl_set_pipe_state(skl, pipe, PPL_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(skl->dev, "Failed to start pipe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) pipe->state = SKL_PIPE_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * Stop the pipeline by sending set pipe state IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * DSP doesnt implement stop so we always send pause message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_dbg(skl->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* If pipe was not created in FW, do not try to pause or delete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (pipe->state < SKL_PIPE_PAUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ret = skl_set_pipe_state(skl, pipe, PPL_PAUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_dbg(skl->dev, "Failed to stop pipe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pipe->state = SKL_PIPE_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * Reset the pipeline by sending set pipe state IPC this will reset the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * from the DSP side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* If pipe was not created in FW, do not try to pause or delete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (pipe->state < SKL_PIPE_PAUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ret = skl_set_pipe_state(skl, pipe, PPL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) dev_dbg(skl->dev, "Failed to reset pipe ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pipe->state = SKL_PIPE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* Algo parameter set helper function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) int skl_set_module_params(struct skl_dev *skl, u32 *params, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 param_id, struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct skl_ipc_large_config_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) msg.module_id = mcfg->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) msg.instance_id = mcfg->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) msg.param_data_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) msg.large_param_id = param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return skl_ipc_set_large_config(&skl->ipc, &msg, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) int skl_get_module_params(struct skl_dev *skl, u32 *params, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) u32 param_id, struct skl_module_cfg *mcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct skl_ipc_large_config_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) size_t bytes = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) msg.module_id = mcfg->id.module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) msg.instance_id = mcfg->id.pvt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) msg.param_data_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) msg.large_param_id = param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return skl_ipc_get_large_config(&skl->ipc, &msg, ¶ms, &bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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