^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl-i2s.h - i2s blob mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Subhransu S. Prusty < subhransu.s.prusty@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SOUND_SOC_SKL_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SOUND_SOC_SKL_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SKL_I2S_MAX_TIME_SLOTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SKL_MCLK_DIV_CLK_SRC_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SKL_MNDSS_DIV_CLK_SRC_MASK GENMASK(21, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SKL_SHIFT(x) (ffs(x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SKL_MCLK_DIV_RATIO_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define is_legacy_blob(x) (x.signature != 0xEE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ext_to_legacy_blob(i2s_config_blob_ext) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ((struct skl_i2s_config_blob_legacy *) i2s_config_blob_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define get_clk_src(mclk, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct skl_i2s_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 ssc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 ssc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 sscto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 sspsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 sstsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 ssrsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 ssc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 sspsp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 ssc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 ssioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct skl_i2s_config_mclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 mdivctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 mdivr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct skl_i2s_config_mclk_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 mdivctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 mdivr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 mdivr[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct skl_i2s_config_blob_signature {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 minor_ver : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 major_ver : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 resvdz : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 signature : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct skl_i2s_config_blob_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct skl_i2s_config_blob_signature sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * struct skl_i2s_config_blob_legacy - Structure defines I2S Gateway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * configuration legacy blob
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @gtw_attr: Gateway attribute for the I2S Gateway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @tdm_ts_group: TDM slot mapping against channels in the Gateway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @i2s_cfg: I2S HW registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @mclk: MCLK clock source and divider values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct skl_i2s_config_blob_legacy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 gtw_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct skl_i2s_config i2s_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct skl_i2s_config_mclk mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct skl_i2s_config_blob_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 gtw_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct skl_i2s_config_blob_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct skl_i2s_config i2s_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct skl_i2s_config_mclk_ext mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif /* __SOUND_SOC_SKL_I2S_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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