Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * cnl-sst.c - DSP library functions for CNL platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016-17, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Guneshwor Singh <guneshwor.o.singh@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Modified from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	HDA DSP library functions for SKL platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Copyright (C) 2014-15, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "../common/sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "cnl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CNL_FW_ROM_INIT		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CNL_FW_INIT		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CNL_IPC_PURGE		0x01004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CNL_INIT_TIMEOUT	300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CNL_BASEFW_TIMEOUT	3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CNL_ADSP_SRAM0_BASE	0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Firmware status window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CNL_ADSP_FW_STATUS	CNL_ADSP_SRAM0_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CNL_ADSP_ERROR_CODE	(CNL_ADSP_FW_STATUS + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CNL_INSTANCE_ID		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CNL_BASE_FW_MODULE_ID	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CNL_ADSP_FW_HDR_OFFSET	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CNL_ROM_CTRL_DMA_ID	0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int cnl_prepare_fw(struct sst_dsp *ctx, const void *fwdata, u32 fwsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int ret, stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (stream_tag <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		dev_err(ctx->dev, "dma prepare failed: 0%#x\n", stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	ctx->dsp_ops.stream_tag = stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	memcpy(ctx->dmab.area, fwdata, fwsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		dev_err(ctx->dev, "dsp core0 power up failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* purge FW request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	sst_dsp_shim_write(ctx, CNL_ADSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			   CNL_ADSP_REG_HIPCIDR_BUSY | (CNL_IPC_PURGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			   ((stream_tag - 1) << CNL_ROM_CTRL_DMA_ID)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ret = sst_dsp_register_poll(ctx, CNL_ADSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				    CNL_ADSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				    CNL_ADSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				    BXT_INIT_TIMEOUT, "HIPCIDA Done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		dev_err(ctx->dev, "timeout for purge request: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	cnl_ipc_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	cnl_ipc_op_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				    CNL_FW_ROM_INIT, CNL_INIT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				    "rom load");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		dev_err(ctx->dev, "rom init timeout, ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) base_fw_load_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				    CNL_FW_INIT, CNL_BASEFW_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				    "firmware boot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int cnl_load_base_firmware(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct firmware stripped_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct skl_dev *cnl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (!ctx->fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			dev_err(ctx->dev, "request firmware failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			goto cnl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* parse uuids if first boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (cnl->is_first_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		ret = snd_skl_parse_uuids(ctx, ctx->fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 					  CNL_ADSP_FW_HDR_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			goto cnl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	stripped_fw.data = ctx->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	stripped_fw.size = ctx->fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	skl_dsp_strip_extended_manifest(&stripped_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		ret = cnl_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_dbg(ctx->dev, "prepare firmware failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		goto cnl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ret = sst_transfer_fw_host_dma(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		dev_err(ctx->dev, "transfer firmware failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		goto cnl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(ctx->dev, "FW ready timed-out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		goto cnl_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	cnl->fw_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cnl_load_base_firmware_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	dev_err(ctx->dev, "firmware load failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	release_firmware(ctx->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ctx->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int cnl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct skl_dev *cnl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct skl_ipc_dxstate_info dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!cnl->fw_loaded) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		cnl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ret = cnl_load_base_firmware(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			dev_err(ctx->dev, "fw reload failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		cnl->cores.state[core_id] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	ret = cnl_dsp_enable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		dev_err(ctx->dev, "enable dsp core %d failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		/* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		cnl_ipc_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		cnl_ipc_op_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		cnl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				"dsp boot timeout, status=%#x error=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				sst_dsp_shim_read(ctx, CNL_ADSP_FW_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		dx.core_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		dx.dx_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				     CNL_BASE_FW_MODULE_ID, &dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			dev_err(ctx->dev, "set_dx failed, core: %d ret: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	cnl->cores.state[core_id] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	cnl_dsp_disable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int cnl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct skl_dev *cnl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct skl_ipc_dxstate_info dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	dx.core_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	dx.dx_mask = SKL_IPC_D3_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			     CNL_BASE_FW_MODULE_ID, &dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			"dsp core %d to d3 failed; continue reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		cnl->fw_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/* disable interrupts if core 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		skl_ipc_op_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		skl_ipc_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ret = cnl_dsp_disable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		dev_err(ctx->dev, "disable dsp core %d failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	cnl->cores.state[core_id] = SKL_DSP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static unsigned int cnl_get_errno(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct skl_dsp_fw_ops cnl_fw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.set_state_D0 = cnl_set_dsp_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.set_state_D3 = cnl_set_dsp_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.load_fw = cnl_load_base_firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.get_fw_errcode = cnl_get_errno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct sst_ops cnl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.irq_handler = cnl_dsp_sst_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.write = sst_shim32_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.read = sst_shim32_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.free = cnl_dsp_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CNL_IPC_GLB_NOTIFY_RSP_SHIFT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CNL_IPC_GLB_NOTIFY_RSP_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CNL_IPC_GLB_NOTIFY_RSP_TYPE(x)	(((x) >> CNL_IPC_GLB_NOTIFY_RSP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					& CNL_IPC_GLB_NOTIFY_RSP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct sst_dsp *dsp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct skl_dev *cnl = dsp->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct sst_generic_ipc *ipc = &cnl->ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct skl_ipc_header header = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u32 hipcida, hipctdr, hipctdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	int ipc_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	/* here we handle ipc interrupts only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!(dsp->intr_status & CNL_ADSPIS_IPC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	hipcida = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	hipctdr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/* reply message from dsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (hipcida & CNL_ADSP_REG_HIPCIDA_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			CNL_ADSP_REG_HIPCCTL_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		/* clear done bit - tell dsp operation is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			CNL_ADSP_REG_HIPCIDA_DONE, CNL_ADSP_REG_HIPCIDA_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ipc_irq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		/* unmask done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			CNL_ADSP_REG_HIPCCTL_DONE, CNL_ADSP_REG_HIPCCTL_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* new message from dsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (hipctdr & CNL_ADSP_REG_HIPCTDR_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		header.primary = hipctdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		header.extension = hipctdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 						header.primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 						header.extension);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		if (CNL_IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			/* Handle Immediate reply from DSP Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			skl_ipc_process_reply(ipc, header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			skl_ipc_process_notification(ipc, header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		/* clear busy interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			CNL_ADSP_REG_HIPCTDR_BUSY, CNL_ADSP_REG_HIPCTDR_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		/* set done bit to ack dsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			CNL_ADSP_REG_HIPCTDA_DONE, CNL_ADSP_REG_HIPCTDA_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ipc_irq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ipc_irq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	cnl_ipc_int_enable(dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	/* continue to send any remaining messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	schedule_work(&ipc->kwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct sst_dsp_device cnl_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.thread = cnl_dsp_irq_thread_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.ops = &cnl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void cnl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->tx.header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (msg->tx.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		sst_dsp_outbox_write(ipc->dsp, msg->tx.data, msg->tx.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 				    header->extension);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 				header->primary | CNL_ADSP_REG_HIPCIDR_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static bool cnl_ipc_is_dsp_busy(struct sst_dsp *dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	u32 hipcidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	hipcidr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	return (hipcidr & CNL_ADSP_REG_HIPCIDR_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int cnl_ipc_init(struct device *dev, struct skl_dev *cnl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	struct sst_generic_ipc *ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	ipc = &cnl->ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	ipc->dsp = cnl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	ipc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	ipc->tx_data_max_size = CNL_ADSP_W1_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	ipc->rx_data_max_size = CNL_ADSP_W0_UP_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	err = sst_ipc_init(ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	 * overriding tx_msg and is_dsp_busy since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	 * ipc registers are different for cnl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	ipc->ops.tx_msg = cnl_ipc_tx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	ipc->ops.is_dsp_busy = cnl_ipc_is_dsp_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		     const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		     struct skl_dev **dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	struct skl_dev *cnl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	struct sst_dsp *sst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &cnl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		dev_err(dev, "%s: no device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	cnl = *dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	sst = cnl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	sst->fw_ops = cnl_fw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	sst->addr.lpe = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	sst->addr.shim = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	sst->addr.sram0_base = CNL_ADSP_SRAM0_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	sst->addr.sram1_base = CNL_ADSP_SRAM1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	sst->addr.w0_stat_sz = CNL_ADSP_W0_STAT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	sst->addr.w0_up_sz = CNL_ADSP_W0_UP_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	sst_dsp_mailbox_init(sst, (CNL_ADSP_SRAM0_BASE + CNL_ADSP_W0_STAT_SZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			     CNL_ADSP_W0_UP_SZ, CNL_ADSP_SRAM1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			     CNL_ADSP_W1_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	ret = cnl_ipc_init(dev, cnl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		skl_dsp_free(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	cnl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	init_waitqueue_head(&cnl->boot_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	return skl_dsp_acquire_irq(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) EXPORT_SYMBOL_GPL(cnl_sst_dsp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct sst_dsp *sst = skl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	ret = skl->dsp->fw_ops.load_fw(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		dev_err(dev, "load base fw failed: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	skl_dsp_init_core_state(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	skl->is_first_boot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) EXPORT_SYMBOL_GPL(cnl_sst_init_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	if (skl->dsp->fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		release_firmware(skl->dsp->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	skl_freeup_uuid_list(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	cnl_ipc_free(&skl->ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	skl->dsp->ops->free(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) EXPORT_SYMBOL_GPL(cnl_sst_dsp_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MODULE_DESCRIPTION("Intel Cannonlake IPC driver");