^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cannonlake SST DSP Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-17, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __CNL_SST_DSP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __CNL_SST_DSP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct sst_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct sst_dsp_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct sst_generic_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Intel HD Audio General DSP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CNL_ADSP_GEN_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CNL_ADSP_REG_ADSPCS (CNL_ADSP_GEN_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CNL_ADSP_REG_ADSPIC (CNL_ADSP_GEN_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CNL_ADSP_REG_ADSPIS (CNL_ADSP_GEN_BASE + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Intel HD Audio Inter-Processor Communication Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CNL_ADSP_IPC_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* HIPCTDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CNL_ADSP_REG_HIPCTDR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* HIPCTDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CNL_ADSP_REG_HIPCTDA_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* HIPCIDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CNL_ADSP_REG_HIPCIDR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* HIPCIDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CNL_ADSP_REG_HIPCIDA_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* CNL HIPCCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CNL_ADSP_REG_HIPCCTL_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CNL_ADSP_REG_HIPCCTL_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* CNL HIPCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CNL_ADSP_REG_HIPCT_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Intel HD Audio SRAM Window 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CNL_ADSP_SRAM1_BASE 0xa0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CNL_ADSP_MMIO_LEN 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CNL_ADSP_W0_STAT_SZ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CNL_ADSP_W0_UP_SZ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CNL_ADSP_W1_SZ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CNL_FW_STS_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CNL_ADSPIC_IPC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CNL_ADSPIS_IPC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CNL_DSP_CORES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* core reset - asserted high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CNL_ADSPCS_CRST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CNL_ADSPCS_CRST(x) (x << CNL_ADSPCS_CRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* core run/stall - when set to 1 core is stalled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CNL_ADSPCS_CSTALL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CNL_ADSPCS_CSTALL(x) (x << CNL_ADSPCS_CSTALL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* set power active - when set to 1 turn core on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CNL_ADSPCS_SPA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CNL_ADSPCS_SPA(x) (x << CNL_ADSPCS_SPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* current power active - power status of cores, set by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CNL_ADSPCS_CPA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CNL_ADSPCS_CPA(x) (x << CNL_ADSPCS_CPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void cnl_dsp_free(struct sst_dsp *dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void cnl_ipc_int_enable(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void cnl_ipc_int_disable(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void cnl_ipc_op_int_enable(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void cnl_ipc_op_int_disable(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bool cnl_ipc_int_status(struct sst_dsp *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void cnl_ipc_free(struct sst_generic_ipc *ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct skl_dev **dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /*__CNL_SST_DSP_H__*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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