^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cnl-sst-dsp.c - CNL SST library generic function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-17, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Guneshwor Singh <guneshwor.o.singh@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Modified from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * SKL SST library generic function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2014-15, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "../common/sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "cnl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* various timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CNL_DSP_PU_TO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNL_DSP_PD_TO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CNL_DSP_RESET_TO 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) cnl_dsp_core_set_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) sst_dsp_shim_update_bits_unlocked(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_CRST(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CNL_ADSPCS_CRST(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CNL_ADSPCS_CRST(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CNL_ADSPCS_CRST(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CNL_DSP_RESET_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "Set reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cnl_dsp_core_unset_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CNL_ADSPCS_CRST(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CNL_ADSPCS_CRST(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CNL_DSP_RESET_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "Unset reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static bool is_cnl_dsp_core_enable(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool is_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) is_enable = (val & CNL_ADSPCS_CPA(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (val & CNL_ADSPCS_SPA(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) !(val & CNL_ADSPCS_CRST(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) !(val & CNL_ADSPCS_CSTALL(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_dbg(ctx->dev, "DSP core(s) enabled? %d: core_mask %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) is_enable, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return is_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int cnl_dsp_reset_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* stall core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CNL_ADSPCS_CSTALL(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CNL_ADSPCS_CSTALL(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* set reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return cnl_dsp_core_set_reset_state(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int cnl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* unset reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = cnl_dsp_core_unset_reset_state(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* run core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CNL_ADSPCS_CSTALL(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!is_cnl_dsp_core_enable(ctx, core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cnl_dsp_reset_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(ctx->dev, "DSP core mask %#x enable failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int cnl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CNL_ADSPCS_SPA(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CNL_ADSPCS_SPA(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return sst_dsp_register_poll(ctx, CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CNL_ADSPCS_CPA(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CNL_ADSPCS_CPA(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CNL_DSP_PU_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "Power up");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int cnl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CNL_ADSPCS_SPA(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return sst_dsp_register_poll(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CNL_ADSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CNL_ADSPCS_CPA(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CNL_DSP_PD_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "Power down");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = cnl_dsp_core_power_up(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_dbg(ctx->dev, "DSP core mask %#x power up failed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return cnl_dsp_start_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = cnl_dsp_reset_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(ctx->dev, "DSP core mask %#x reset failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* power down core*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = cnl_dsp_core_power_down(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(ctx->dev, "DSP core mask %#x power down failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (is_cnl_dsp_core_enable(ctx, core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(ctx->dev, "DSP core mask %#x disable failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct sst_dsp *ctx = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_lock(&ctx->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ctx->intr_status = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (val == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spin_unlock(&ctx->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (val & CNL_ADSPIS_IPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cnl_ipc_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spin_unlock(&ctx->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void cnl_dsp_free(struct sst_dsp *dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cnl_ipc_int_disable(dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) free_irq(dsp->irq, dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cnl_ipc_op_int_disable(dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cnl_dsp_disable_core(dsp, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) EXPORT_SYMBOL_GPL(cnl_dsp_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void cnl_ipc_int_enable(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_ADSPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CNL_ADSPIC_IPC, CNL_ADSPIC_IPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void cnl_ipc_int_disable(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CNL_ADSPIC_IPC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void cnl_ipc_op_int_enable(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* enable IPC DONE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CNL_ADSP_REG_HIPCCTL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CNL_ADSP_REG_HIPCCTL_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* enable IPC BUSY interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CNL_ADSP_REG_HIPCCTL_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CNL_ADSP_REG_HIPCCTL_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void cnl_ipc_op_int_disable(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* disable IPC DONE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CNL_ADSP_REG_HIPCCTL_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* disable IPC BUSY interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CNL_ADSP_REG_HIPCCTL_BUSY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bool cnl_ipc_int_status(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CNL_ADSPIS_IPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void cnl_ipc_free(struct sst_generic_ipc *ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cnl_ipc_op_int_disable(ipc->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sst_ipc_fini(ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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