^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bxt-sst.c - DSP library functions for BXT platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-16 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "../common/sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../common/sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BXT_BASEFW_TIMEOUT 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BXT_ROM_INIT_TIMEOUT 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BXT_IPC_PURGE_FW 0x01004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BXT_ROM_INIT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BXT_ADSP_SRAM0_BASE 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Firmware status window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BXT_ADSP_SRAM1_BASE 0xA0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BXT_INSTANCE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BXT_BASE_FW_MODULE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Delay before scheduling D0i3 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BXT_D0I3_DELAY 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_dma_buffer dmab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct firmware stripped_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int ret = 0, i, dma_id, stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* library indices start from 1 to N. 0 represents base FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) for (i = 1; i < lib_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) BXT_ADSP_FW_BIN_HDR_OFFSET, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) goto load_library_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) stripped_fw.size, &dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (stream_tag <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) goto load_library_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dma_id = stream_tag - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) linfo[i].name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) load_library_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) skl_release_library(linfo, lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * First boot sequence has some extra steps. Core 0 waits for power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * status on core 1, so power up core 1 also momentarily, keep it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * reset/stall and then turn it off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const void *fwdata, u32 fwsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int stream_tag, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (stream_tag <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ctx->dsp_ops.stream_tag = stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) memcpy(ctx->dmab.area, fwdata, fwsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Step 1: Power up core 0 and core1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SKL_DSP_CORE_MASK(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(ctx->dev, "dsp core0/1 power up failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Step 2: Purge FW request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Step 3: Unset core0 reset state & unstall/run core0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Step 4: Wait for DONE Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SKL_ADSP_REG_HIPCIE_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SKL_ADSP_REG_HIPCIE_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BXT_INIT_TIMEOUT, "HIPCIE Done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Step 5: power down core1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(ctx->dev, "dsp core1 power down failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Step 6: Enable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) skl_ipc_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) skl_ipc_op_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Step 7: Wait for ROM init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto base_fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) base_fw_load_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int bxt_load_base_firmware(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct firmware stripped_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ctx->fw == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(ctx->dev, "Request firmware failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* prase uuids on first boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (skl->is_first_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto sst_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stripped_fw.data = ctx->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) stripped_fw.size = ctx->fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) skl_dsp_strip_extended_manifest(&stripped_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) goto sst_load_base_firmware_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = sst_transfer_fw_host_dma(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(ctx->dev, "Firmware download successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) skl->fw_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sst_load_base_firmware_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) release_firmware(ctx->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ctx->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Decide the D0i3 state that can be targeted based on the usecase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * ref counts and DSP state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Decision Matrix: (X= dont care; state = target state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * DSP state != SKL_DSP_RUNNING ; state = no d0i3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * DSP state == SKL_DSP_RUNNING , the following matrix applies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int bxt_d0i3_target_state(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct skl_d0i3_data *d0i3 = &skl->d0i3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return SKL_DSP_D0I3_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (d0i3->non_d0i3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return SKL_DSP_D0I3_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else if (d0i3->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return SKL_DSP_D0I3_STREAMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else if (d0i3->non_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return SKL_DSP_D0I3_NON_STREAMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return SKL_DSP_D0I3_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void bxt_set_dsp_D0i3(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct skl_ipc_d0ix_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct skl_dev *skl = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct skl_dev, d0i3.work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct sst_dsp *ctx = skl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct skl_d0i3_data *d0i3 = &skl->d0i3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_dbg(ctx->dev, "In %s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* D0i3 entry allowed only if core 0 alone is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_warn(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "D0i3 allowed when only core0 running:Exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) target_state = bxt_d0i3_target_state(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (target_state == SKL_DSP_D0I3_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) msg.instance_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) msg.module_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) msg.wake = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) msg.streaming = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (target_state == SKL_DSP_D0I3_STREAMING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) msg.streaming = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Set Vendor specific register D0I3C.I3 to enable D0i3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (skl->update_d0i3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) skl->update_d0i3c(skl->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) d0i3->state = target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct skl_d0i3_data *d0i3 = &skl->d0i3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Schedule D0i3 only if the usecase ref counts are appropriate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) schedule_delayed_work(&d0i3->work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) msecs_to_jiffies(BXT_D0I3_DELAY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct skl_ipc_d0ix_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_dbg(ctx->dev, "In %s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* First Cancel any pending attempt to put DSP to D0i3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cancel_delayed_work_sync(&skl->d0i3.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* If DSP is currently in D0i3, bring it to D0i0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_dbg(ctx->dev, "Set DSP to D0i0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msg.instance_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) msg.module_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg.streaming = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg.wake = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msg.streaming = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (skl->update_d0i3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) skl->update_d0i3c(skl->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) skl->d0i3.state = SKL_DSP_D0I3_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct skl_ipc_dxstate_info dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (skl->fw_loaded == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) skl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = bxt_load_base_firmware(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(ctx->dev, "reload fw failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (skl->lib_count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = bxt_load_library(ctx, skl->lib_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) skl->lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(ctx->dev, "reload libs failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) skl->cores.state[core_id] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* If core 0 is being turned on, turn on core 1 as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (core_id == SKL_DSP_CORE0_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = skl_dsp_core_power_up(ctx, core_mask |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SKL_DSP_CORE_MASK(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = skl_dsp_core_power_up(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Enable interrupt after SPA is set and before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * DSP is unstalled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) skl_ipc_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) skl_ipc_op_int_enable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) skl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = skl_dsp_start_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = wait_event_timeout(skl->boot_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) skl->boot_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* If core 1 was turned on for booting core 0, turn it off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Tell FW if additional core in now On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (core_id != SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dx.core_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dx.dx_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BXT_BASE_FW_MODULE_ID, &dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) core_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) skl->cores.state[core_id] = SKL_DSP_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (core_id == SKL_DSP_CORE0_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) core_mask |= SKL_DSP_CORE_MASK(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) skl_dsp_disable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct skl_ipc_dxstate_info dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct skl_dev *skl = ctx->thread_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dx.core_mask = core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dx.dx_mask = SKL_IPC_D3_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dx.core_mask, dx.dx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) BXT_BASE_FW_MODULE_ID, &dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "Failed to set DSP to D3:core id = %d;Continue reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * In case of D3 failure, re-download the firmware, so set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * fw_loaded to false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) skl->fw_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (core_id == SKL_DSP_CORE0_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* disable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) skl_ipc_op_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) skl_ipc_int_disable(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = skl_dsp_disable_core(ctx, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(ctx->dev, "Failed to disable core %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) skl->cores.state[core_id] = SKL_DSP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const struct skl_dsp_fw_ops bxt_fw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .set_state_D0 = bxt_set_dsp_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .set_state_D3 = bxt_set_dsp_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .set_state_D0i3 = bxt_schedule_dsp_D0i3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .set_state_D0i0 = bxt_set_dsp_D0i0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .load_fw = bxt_load_base_firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .get_fw_errcode = bxt_get_errorcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .load_library = bxt_load_library,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct sst_ops skl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .irq_handler = skl_dsp_sst_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .write = sst_shim32_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .read = sst_shim32_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .free = skl_dsp_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct sst_dsp_device skl_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .thread = skl_dsp_irq_thread_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .ops = &skl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct skl_dev **dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct skl_dev *skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct sst_dsp *sst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_err(dev, "%s: no device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) skl = *dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sst = skl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sst->fw_ops = bxt_fw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) sst->addr.lpe = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sst->addr.shim = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = skl_ipc_init(dev, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) skl_dsp_free(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* set the D0i3 check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) skl->boot_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) init_waitqueue_head(&skl->boot_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) skl->d0i3.state = SKL_DSP_D0I3_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return skl_dsp_acquire_irq(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct sst_dsp *sst = skl->dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = sst->fw_ops.load_fw(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_err(dev, "Load base fw failed: %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) skl_dsp_init_core_state(sst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (skl->lib_count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = sst->fw_ops.load_library(sst, skl->lib_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) skl->lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(dev, "Load Library failed : %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) skl->is_first_boot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) skl_release_library(skl->lib_info, skl->lib_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (skl->dsp->fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) release_firmware(skl->dsp->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) skl_freeup_uuid_list(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) skl_ipc_free(&skl->ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) skl->dsp->ops->free(skl->dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MODULE_DESCRIPTION("Intel Broxton IPC driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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