^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Smart Sound Technology (SST) DSP Core Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013, Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sst-dsp-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <trace/events/intel-sst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Internal generic low-level SST IO functions - can be overidden */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) writel(value, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) EXPORT_SYMBOL_GPL(sst_shim32_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 sst_shim32_read(void __iomem *addr, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return readl(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) EXPORT_SYMBOL_GPL(sst_shim32_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) writeq(value, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) EXPORT_SYMBOL_GPL(sst_shim32_write64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u64 sst_shim32_read64(void __iomem *addr, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return readq(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) EXPORT_SYMBOL_GPL(sst_shim32_read64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Public API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) spin_lock_irqsave(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sst->ops->write(sst->addr.shim, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spin_unlock_irqrestore(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EXPORT_SYMBOL_GPL(sst_dsp_shim_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) spin_lock_irqsave(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = sst->ops->read(sst->addr.shim, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spin_unlock_irqrestore(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) EXPORT_SYMBOL_GPL(sst_dsp_shim_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sst->ops->write(sst->addr.shim, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return sst->ops->read(sst->addr.shim, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = sst_dsp_shim_read_unlocked(sst, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) old = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) new = (old & (~mask)) | (value & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) change = (old != new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sst_dsp_shim_write_unlocked(sst, offset, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* This is for registers bits with attribute RWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = sst_dsp_shim_read_unlocked(sst, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) old = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) new = (old & (~mask)) | (value & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sst_dsp_shim_write_unlocked(sst, offset, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) spin_lock_irqsave(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) spin_unlock_irqrestore(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* This is for registers bits with attribute RWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spin_lock_irqsave(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) spin_unlock_irqrestore(&sst->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 target, u32 time, char *operation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int k = 0, s = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * split the loop into sleeps of varying resolution. more accurately,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * the range of wakeups are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * (usleep_range (500, 1000) and usleep_range(5000, 10000) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * both possible in this phase depending on whether k > 10 or not).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) timeout = jiffies + msecs_to_jiffies(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) && time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) k++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (k > 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) s = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) usleep_range(s, 2*s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if ((reg & mask) == target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg, operation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg, operation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 outbox_offset, size_t outbox_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sst->mailbox.in_size = inbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sst->mailbox.out_size = outbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) trace_sst_ipc_outbox_write(bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) memcpy_toio(sst->mailbox.out_base, message, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (i = 0; i < bytes; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) trace_sst_ipc_outbox_read(bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) memcpy_fromio(message, sst->mailbox.out_base, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < bytes; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) trace_sst_ipc_inbox_write(bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) memcpy_toio(sst->mailbox.in_base, message, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < bytes; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) trace_sst_ipc_inbox_read(bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) memcpy_fromio(message, sst->mailbox.in_base, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) for (i = 0; i < bytes; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_AUTHOR("Liam Girdwood");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_DESCRIPTION("Intel SST Core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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