Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright(c) 2020 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Cezary Rojewski <cezary.rojewski@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __SND_SOC_INTEL_CATPT_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __SND_SOC_INTEL_CATPT_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <uapi/linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CATPT_SHIM_REGS_SIZE	4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CATPT_DMA_REGS_SIZE	1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CATPT_DMA_COUNT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CATPT_SSP_REGS_SIZE	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* DSP Shim registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CATPT_SHIM_CS1		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CATPT_SHIM_ISC		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CATPT_SHIM_ISD		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CATPT_SHIM_IMC		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CATPT_SHIM_IMD		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CATPT_SHIM_IPCC		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CATPT_SHIM_IPCD		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CATPT_SHIM_CLKCTL	0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CATPT_SHIM_CS2		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CATPT_SHIM_LTRC		0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CATPT_SHIM_HMDC		0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CATPT_CS_LPCS		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CATPT_CS_SFCR(ssp)	BIT(27 + (ssp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CATPT_CS_S1IOCS		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CATPT_CS_S0IOCS		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CATPT_CS_PCE		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CATPT_CS_SDPM(ssp)	BIT(11 + (ssp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CATPT_CS_STALL		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CATPT_CS_DCS		GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* b100 DSP core & audio fabric high clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CATPT_CS_DCS_HIGH	(0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CATPT_CS_SBCS(ssp)	BIT(2 + (ssp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CATPT_CS_RST		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CATPT_ISC_IPCDB		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CATPT_ISC_IPCCD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CATPT_ISD_DCPWM		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CATPT_ISD_IPCCB		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CATPT_ISD_IPCDD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CATPT_IMC_IPCDB		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CATPT_IMC_IPCCD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CATPT_IMD_IPCCB		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CATPT_IMD_IPCDD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CATPT_IPCC_BUSY		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CATPT_IPCC_DONE		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CATPT_IPCD_BUSY		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CATPT_IPCD_DONE		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CATPT_CLKCTL_CFCIP	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CATPT_CLKCTL_SMOS	GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CATPT_HMDC_HDDA(e, ch)	BIT(8 * (e) + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* defaults to reset SHIM registers to after each power cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CATPT_CS_DEFAULT	0x8480040E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CATPT_ISC_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CATPT_ISD_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CATPT_IMC_DEFAULT	0x7FFF0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CATPT_IMD_DEFAULT	0x7FFF0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CATPT_IPCC_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CATPT_IPCD_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CATPT_CLKCTL_DEFAULT	0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CATPT_CS2_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CATPT_LTRC_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CATPT_HMDC_DEFAULT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* PCI Configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CATPT_PCI_PMCAPID	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CATPT_PCI_PMCS		(CATPT_PCI_PMCAPID + PCI_PM_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CATPT_PCI_VDRTCTL0	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CATPT_PCI_VDRTCTL2	0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CATPT_VDRTCTL2_DTCGE	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CATPT_VDRTCTL2_DCLCGE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CATPT_VDRTCTL2_CGEALL	0xF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* LPT PCI Configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define LPT_VDRTCTL0_DSRAMPGE(b)	BIT(16 + (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define LPT_VDRTCTL0_DSRAMPGE_MASK	GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define LPT_VDRTCTL0_ISRAMPGE(b)	BIT(6 + (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define LPT_VDRTCTL0_ISRAMPGE_MASK	GENMASK(15, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define LPT_VDRTCTL0_D3SRAMPGD		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define LPT_VDRTCTL0_D3PGD		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LPT_VDRTCTL0_APLLSE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* WPT PCI Configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WPT_VDRTCTL0_DSRAMPGE(b)	BIT(12 + (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WPT_VDRTCTL0_DSRAMPGE_MASK	GENMASK(31, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WPT_VDRTCTL0_ISRAMPGE(b)	BIT(2 + (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WPT_VDRTCTL0_ISRAMPGE_MASK	GENMASK(11, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WPT_VDRTCTL0_D3SRAMPGD		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WPT_VDRTCTL0_D3PGD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WPT_VDRTCTL2_APLLSE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* defaults to reset SSP registers to after each power cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CATPT_SSC0_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CATPT_SSC1_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CATPT_SSS_DEFAULT		0xF004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CATPT_SSIT_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CATPT_SSD_DEFAULT		0xC43893A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CATPT_SSTO_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CATPT_SSPSP_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CATPT_SSTSA_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CATPT_SSRSA_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CATPT_SSTSS_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CATPT_SSCR2_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CATPT_SSPSP2_DEFAULT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Physically the same block, access address differs between host and dsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CATPT_DSP_DRAM_OFFSET		0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define catpt_to_host_offset(offset)	((offset) & ~(CATPT_DSP_DRAM_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define catpt_to_dsp_offset(offset)	((offset) | CATPT_DSP_DRAM_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CATPT_MEMBLOCK_SIZE	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define catpt_num_dram(cdev)	(hweight_long((cdev)->spec->dram_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define catpt_num_iram(cdev)	(hweight_long((cdev)->spec->iram_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define catpt_dram_size(cdev)	(catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define catpt_iram_size(cdev)	(catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* registry I/O helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define catpt_shim_addr(cdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	((cdev)->lpe_ba + (cdev)->spec->host_shim_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define catpt_dma_addr(cdev, dma) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define catpt_ssp_addr(cdev, ssp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define catpt_inbox_addr(cdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define catpt_outbox_addr(cdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define catpt_writel_ssp(cdev, ssp, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define catpt_readl_shim(cdev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define catpt_writel_shim(cdev, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define catpt_updatel_shim(cdev, reg, mask, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	catpt_writel_shim(cdev, reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			  (catpt_readl_shim(cdev, reg) & ~(mask)) | (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			   val, cond, delay_us, timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define catpt_readl_pci(cdev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	readl(cdev->pci_ba + CATPT_PCI_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define catpt_writel_pci(cdev, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	writel(val, cdev->pci_ba + CATPT_PCI_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define catpt_updatel_pci(cdev, reg, mask, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	catpt_writel_pci(cdev, reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			 (catpt_readl_pci(cdev, reg) & ~(mask)) | (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			   val, cond, delay_us, timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif