^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright(c) 2020 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Cezary Rojewski <cezary.rojewski@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/devcoredump.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pxa2xx_ssp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "messages.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "registers.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static bool catpt_dma_filter(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) return param == chan->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Either engine 0 or 1 can be used for image loading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Align with Windows driver equivalent and stick to engine 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CATPT_DMA_DEVID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CATPT_DMA_DSP_ADDR_MASK GENMASK(31, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dma_cap_set(DMA_MEMCPY, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_err(cdev->dev, "request channel failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) memset(&config, 0, sizeof(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) config.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) config.src_maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) config.dst_maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = dmaengine_slave_config(chan, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_err(cdev->dev, "slave config failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int catpt_dma_memcpy(struct catpt_dev *cdev, struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dma_addr_t dst_addr, dma_addr_t src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) desc = dmaengine_prep_dma_memcpy(chan, dst_addr, src_addr, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_err(cdev->dev, "prep dma memcpy failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* enable demand mode for dma channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) catpt_updatel_shim(cdev, HMDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = dma_submit_error(dmaengine_submit(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(cdev->dev, "submit tx failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto clear_hdda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) status = dma_wait_for_async_tx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = (status == DMA_COMPLETE) ? 0 : -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clear_hdda:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* regardless of status, disable access to HOST memory in demand mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) catpt_updatel_shim(cdev, HMDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_addr_t dst_addr, dma_addr_t src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return catpt_dma_memcpy(cdev, chan, dst_addr | CATPT_DMA_DSP_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) src_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma_addr_t dst_addr, dma_addr_t src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return catpt_dma_memcpy(cdev, chan, dst_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) src_addr | CATPT_DMA_DSP_ADDR_MASK, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int catpt_dmac_probe(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct dw_dma_chip *dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dmac = devm_kzalloc(cdev->dev, sizeof(*dmac), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!dmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dmac->regs = cdev->lpe_ba + cdev->spec->host_dma_offset[CATPT_DMA_DEVID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dmac->dev = cdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dmac->irq = cdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = dma_coerce_mask_and_coherent(cdev->dev, DMA_BIT_MASK(31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Caller is responsible for putting device in D0 to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * for I/O and memory access before probing DW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = dw_dma_probe(dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cdev->dmac = dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void catpt_dmac_remove(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * As do_dma_remove() juggles with pm_runtime_get_xxx() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * pm_runtime_put_xxx() while both ADSP and DW 'devices' are part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * the same module, caller makes sure pm_runtime_disable() is invoked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * before removing DW to prevent postmortem resume and suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dw_dma_remove(cdev->dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void catpt_dsp_set_srampge(struct catpt_dev *cdev, struct resource *sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long mask, unsigned long new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 off = sram->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 b = __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) old = catpt_readl_pci(cdev, VDRTCTL0) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_dbg(cdev->dev, "SRAMPGE [0x%08lx] 0x%08lx -> 0x%08lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mask, old, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (old == new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) catpt_updatel_pci(cdev, VDRTCTL0, mask, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* wait for SRAM power gating to propagate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) udelay(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Dummy read as the very first access after block enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * to prevent byte loss in future operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for_each_clear_bit_from(b, &new, fls_long(mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* newly enabled: new bit=0 while old bit=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (test_bit(b, &old)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(cdev->dev, "sanitize block %ld: off 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) b - __ffs(mask), off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) memcpy_fromio(buf, cdev->lpe_ba + off, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) off += CATPT_MEMBLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long new = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* flag all busy blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (res = sram->child; res; res = res->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 h, l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) h = (res->end - sram->start) / CATPT_MEMBLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) l = (res->start - sram->start) / CATPT_MEMBLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) new |= GENMASK(h, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* offset value given mask's start and invert it as ON=b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) new = ~(new << __ffs(mask)) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* disable core clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) catpt_dsp_set_srampge(cdev, sram, mask, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* enable core clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CATPT_VDRTCTL2_DCLCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int catpt_dsp_stall(struct catpt_dev *cdev, bool stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val = stall ? CATPT_CS_STALL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return catpt_readl_poll_shim(cdev, CS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg, (reg & CATPT_CS_STALL) == val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 500, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int catpt_dsp_reset(struct catpt_dev *cdev, bool reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val = reset ? CATPT_CS_RST : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return catpt_readl_poll_shim(cdev, CS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reg, (reg & CATPT_CS_RST) == val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 500, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val = enable ? LPT_VDRTCTL0_APLLSE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = enable ? WPT_VDRTCTL2_APLLSE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 mask, reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mutex_lock(&cdev->clk_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val = lp ? CATPT_CS_LPCS : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_dbg(cdev->dev, "LPCS [0x%08lx] 0x%08x -> 0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CATPT_CS_LPCS, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (reg == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mutex_unlock(&cdev->clk_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (waiti) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* wait for DSP to signal WAIT state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = catpt_readl_poll_shim(cdev, ISD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg, (reg & CATPT_ISD_DCPWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 500, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_warn(cdev->dev, "await WAITI timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* no signal - only high clock selection allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mutex_unlock(&cdev->clk_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = catpt_readl_poll_shim(cdev, CLKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) reg, !(reg & CATPT_CLKCTL_CFCIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 500, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_warn(cdev->dev, "clock change still in progress\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* default to DSP core & audio fabric high clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) val |= CATPT_CS_DCS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mask = CATPT_CS_LPCS | CATPT_CS_DCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) catpt_updatel_shim(cdev, CS1, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = catpt_readl_poll_shim(cdev, CLKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) reg, !(reg & CATPT_CLKCTL_CFCIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 500, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_warn(cdev->dev, "clock change still in progress\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* update PLL accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) cdev->spec->pll_shutdown(cdev, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_unlock(&cdev->clk_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int catpt_dsp_update_lpclock(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct catpt_stream_runtime *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) list_for_each_entry(stream, &cdev->stream_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (stream->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return catpt_dsp_select_lpclock(cdev, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return catpt_dsp_select_lpclock(cdev, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* bring registers to their defaults as HW won't reset itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) catpt_writel_shim(cdev, ISC, CATPT_ISC_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) catpt_writel_shim(cdev, ISD, CATPT_ISD_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) catpt_writel_shim(cdev, IMC, CATPT_IMC_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) catpt_writel_shim(cdev, IMD, CATPT_IMD_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) catpt_writel_shim(cdev, IPCD, CATPT_IPCD_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) catpt_writel_shim(cdev, CLKCTL, CATPT_CLKCTL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) catpt_writel_shim(cdev, CS2, CATPT_CS2_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) catpt_writel_shim(cdev, LTRC, CATPT_LTRC_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) catpt_writel_shim(cdev, HMDC, CATPT_HMDC_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for (i = 0; i < CATPT_SSP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) catpt_writel_ssp(cdev, i, SSCR0, CATPT_SSC0_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) catpt_writel_ssp(cdev, i, SSCR1, CATPT_SSC1_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) catpt_writel_ssp(cdev, i, SSITR, CATPT_SSIT_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) catpt_writel_ssp(cdev, i, SSDR, CATPT_SSD_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) catpt_writel_ssp(cdev, i, SSTO, CATPT_SSTO_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) catpt_writel_ssp(cdev, i, SSPSP, CATPT_SSPSP_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) catpt_writel_ssp(cdev, i, SSTSA, CATPT_SSTSA_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) catpt_writel_ssp(cdev, i, SSRSA, CATPT_SSRSA_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) catpt_writel_ssp(cdev, i, SSTSS, CATPT_SSTSS_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) catpt_writel_ssp(cdev, i, SSCR2, CATPT_SSCR2_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) catpt_writel_ssp(cdev, i, SSPSP2, CATPT_SSPSP2_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int lpt_dsp_power_down(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) catpt_dsp_reset(cdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* set 24Mhz clock for both SSPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) catpt_dsp_select_lpclock(cdev, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* DRAM power gating all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cdev->spec->dram_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cdev->spec->iram_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* give hw time to drop off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int lpt_dsp_power_up(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* SRAM power gating none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* give hw time to wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) catpt_dsp_select_lpclock(cdev, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) catpt_updatel_shim(cdev, CS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* stagger DSP reset after clock selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) catpt_dsp_reset(cdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* generate int deassert msg to fix inversed int logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int wpt_dsp_power_down(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* disable core clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) catpt_dsp_reset(cdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* set 24Mhz clock for both SSPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) catpt_dsp_select_lpclock(cdev, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* disable MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) catpt_dsp_set_regs_defaults(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* switch clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val = mask & (~CATPT_VDRTCTL2_DTCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) catpt_updatel_pci(cdev, VDRTCTL2, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* enable DTCGE separatelly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CATPT_VDRTCTL2_DTCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* SRAM power gating all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cdev->spec->dram_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) cdev->spec->iram_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mask = WPT_VDRTCTL0_D3SRAMPGD | WPT_VDRTCTL0_D3PGD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) catpt_updatel_pci(cdev, VDRTCTL0, mask, WPT_VDRTCTL0_D3PGD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* give hw time to drop off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* enable core clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CATPT_VDRTCTL2_DCLCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int wpt_dsp_power_up(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* disable core clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* switch clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val = mask & (~CATPT_VDRTCTL2_DTCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) catpt_updatel_pci(cdev, VDRTCTL2, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* SRAM power gating none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mask = WPT_VDRTCTL0_D3SRAMPGD | WPT_VDRTCTL0_D3PGD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) catpt_updatel_pci(cdev, VDRTCTL0, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) catpt_dsp_set_regs_defaults(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* restore MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, CATPT_CLKCTL_SMOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) catpt_dsp_select_lpclock(cdev, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* set 24Mhz clock for both SSPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) catpt_dsp_reset(cdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* enable core clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CATPT_VDRTCTL2_DCLCGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* generate int deassert msg to fix inversed int logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define CATPT_DUMP_MAGIC 0xcd42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define CATPT_DUMP_SECTION_ID_FILE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define CATPT_DUMP_SECTION_ID_IRAM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CATPT_DUMP_SECTION_ID_DRAM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define CATPT_DUMP_SECTION_ID_REGS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CATPT_DUMP_HASH_SIZE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct catpt_dump_section_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u16 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 section_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int catpt_coredump(struct catpt_dev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct catpt_dump_section_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) size_t dump_size, regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 *dump, *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const char *eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) char *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regs_size = CATPT_SHIM_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regs_size += CATPT_DMA_COUNT * CATPT_DMA_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regs_size += CATPT_SSP_COUNT * CATPT_SSP_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dump_size = resource_size(&cdev->dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dump_size += resource_size(&cdev->iram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dump_size += regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* account for header of each section and hash chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dump_size += 4 * sizeof(*hdr) + CATPT_DUMP_HASH_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dump = vzalloc(dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!dump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pos = dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hdr = (struct catpt_dump_section_hdr *)pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hdr->magic = CATPT_DUMP_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hdr->core_id = cdev->spec->core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hdr->section_id = CATPT_DUMP_SECTION_ID_FILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hdr->size = dump_size - sizeof(*hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pos += sizeof(*hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) info = cdev->ipc.config.fw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) eof = info + FW_INFO_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* navigate to fifth info segment (fw hash) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (i = 0; i < 4 && info < eof; i++, info++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* info segments are separated by space each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) info = strnchr(info, eof - info, ' ');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (i == 4 && info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) memcpy(pos, info, min_t(u32, eof - info, CATPT_DUMP_HASH_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pos += CATPT_DUMP_HASH_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hdr = (struct catpt_dump_section_hdr *)pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hdr->magic = CATPT_DUMP_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) hdr->core_id = cdev->spec->core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hdr->section_id = CATPT_DUMP_SECTION_ID_IRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hdr->size = resource_size(&cdev->iram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pos += sizeof(*hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) memcpy_fromio(pos, cdev->lpe_ba + cdev->iram.start, hdr->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pos += hdr->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) hdr = (struct catpt_dump_section_hdr *)pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hdr->magic = CATPT_DUMP_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hdr->core_id = cdev->spec->core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hdr->section_id = CATPT_DUMP_SECTION_ID_DRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hdr->size = resource_size(&cdev->dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pos += sizeof(*hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) memcpy_fromio(pos, cdev->lpe_ba + cdev->dram.start, hdr->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pos += hdr->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hdr = (struct catpt_dump_section_hdr *)pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) hdr->magic = CATPT_DUMP_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) hdr->core_id = cdev->spec->core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) hdr->section_id = CATPT_DUMP_SECTION_ID_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hdr->size = regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pos += sizeof(*hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) memcpy_fromio(pos, catpt_shim_addr(cdev), CATPT_SHIM_REGS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pos += CATPT_SHIM_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for (i = 0; i < CATPT_SSP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) memcpy_fromio(pos, catpt_ssp_addr(cdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CATPT_SSP_REGS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pos += CATPT_SSP_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < CATPT_DMA_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) memcpy_fromio(pos, catpt_dma_addr(cdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CATPT_DMA_REGS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pos += CATPT_DMA_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_coredumpv(cdev->dev, dump, dump_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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