Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * IMG SPDIF output controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Damien Horsley <Damien.Horsley@imgtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMG_SPDIF_OUT_TX_FIFO		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IMG_SPDIF_OUT_CTL		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMG_SPDIF_OUT_CTL_FS_MASK	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMG_SPDIF_OUT_CTL_CLK_MASK	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMG_SPDIF_OUT_CTL_SRT_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMG_SPDIF_OUT_CSL		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IMG_SPDIF_OUT_CSH_UV		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMG_SPDIF_OUT_CSH_UV_CSH_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct img_spdif_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct clk *clk_sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct snd_dmaengine_dai_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 suspend_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 suspend_csl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 suspend_csh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int img_spdif_out_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct img_spdif_out *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	clk_disable_unprepare(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	clk_disable_unprepare(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int img_spdif_out_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct img_spdif_out *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ret = clk_prepare_enable(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ret = clk_prepare_enable(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		clk_disable_unprepare(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	writel(val, spdif->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return readl(spdif->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void img_spdif_out_reset(struct img_spdif_out *spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 ctl, status_low, status_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			~IMG_SPDIF_OUT_CTL_SRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	status_low = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	status_high = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	reset_control_assert(spdif->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	reset_control_deassert(spdif->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	img_spdif_out_writel(spdif, ctl, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	img_spdif_out_writel(spdif, status_low, IMG_SPDIF_OUT_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	img_spdif_out_writel(spdif, status_high, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int img_spdif_out_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 					struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int img_spdif_out_get_status_mask(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				       struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ucontrol->value.iec958.status[4] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int img_spdif_out_get_status(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				  struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ucontrol->value.iec958.status[0] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ucontrol->value.iec958.status[4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		(reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int img_spdif_out_set_status(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				  struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	reg = ((u32)ucontrol->value.iec958.status[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	reg |= ((u32)ucontrol->value.iec958.status[2] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	reg |= ((u32)ucontrol->value.iec958.status[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	reg |= (u32)ucontrol->value.iec958.status[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	reg |= (u32)ucontrol->value.iec958.status[4] <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct snd_kcontrol_new img_spdif_out_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.info = img_spdif_out_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.get = img_spdif_out_get_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.info = img_spdif_out_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.get = img_spdif_out_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.put = img_spdif_out_set_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int img_spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		reg |= IMG_SPDIF_OUT_CTL_SRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		img_spdif_out_reset(spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int img_spdif_out_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned int channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	snd_pcm_format_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			rate, channels, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (format != SNDRV_PCM_FORMAT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (channels != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (pre_div_a < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return pre_div_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (pre_div_b < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return pre_div_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	diff_a = abs((pre_div_a / 256) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	diff_b = abs((pre_div_b / 384) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* If diffs are equal, use lower clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (diff_a > diff_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		clk_set_rate(spdif->clk_ref, pre_div_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		clk_set_rate(spdif->clk_ref, pre_div_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 * Another driver (eg machine driver) may have rejected the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * change. Get the current rate and set the register bit according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 * the new min diff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	clk_rate = clk_get_rate(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	diff_a = abs((clk_rate / 256) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	diff_b = abs((clk_rate / 384) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (diff_a <= diff_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		reg |= IMG_SPDIF_OUT_CTL_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct snd_soc_dai_ops img_spdif_out_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.trigger = img_spdif_out_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.hw_params = img_spdif_out_hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int img_spdif_out_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	snd_soc_add_dai_controls(dai, img_spdif_out_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			ARRAY_SIZE(img_spdif_out_controls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct snd_soc_dai_driver img_spdif_out_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.probe = img_spdif_out_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.formats = SNDRV_PCM_FMTBIT_S32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.ops = &img_spdif_out_dai_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct snd_soc_component_driver img_spdif_out_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.name = "img-spdif-out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int img_spdif_out_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct img_spdif_out *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	platform_set_drvdata(pdev, spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	spdif->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	spdif->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	spdif->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (IS_ERR(spdif->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		if (PTR_ERR(spdif->rst) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			dev_err(&pdev->dev, "No top level reset found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return PTR_ERR(spdif->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (IS_ERR(spdif->clk_sys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		if (PTR_ERR(spdif->clk_sys) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			dev_err(dev, "Failed to acquire clock 'sys'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return PTR_ERR(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (IS_ERR(spdif->clk_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		if (PTR_ERR(spdif->clk_ref) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			dev_err(dev, "Failed to acquire clock 'ref'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return PTR_ERR(spdif->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = img_spdif_out_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			     IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	img_spdif_out_reset(spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	spin_lock_init(&spdif->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	spdif->dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	spdif->dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			&img_spdif_out_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			&img_spdif_out_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	dev_dbg(&pdev->dev, "Probe successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		img_spdif_out_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int img_spdif_out_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		img_spdif_out_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int img_spdif_out_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	struct img_spdif_out *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	if (pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		ret = img_spdif_out_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	spdif->suspend_ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	spdif->suspend_csl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	spdif->suspend_csh = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	img_spdif_out_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int img_spdif_out_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct img_spdif_out *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	ret = img_spdif_out_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	img_spdif_out_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	img_spdif_out_writel(spdif, spdif->suspend_csl, IMG_SPDIF_OUT_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	img_spdif_out_writel(spdif, spdif->suspend_csh, IMG_SPDIF_OUT_CSH_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		img_spdif_out_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct of_device_id img_spdif_out_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	{ .compatible = "img,spdif-out" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_DEVICE_TABLE(of, img_spdif_out_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct dev_pm_ops img_spdif_out_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	SET_RUNTIME_PM_OPS(img_spdif_out_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			   img_spdif_out_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	SET_SYSTEM_SLEEP_PM_OPS(img_spdif_out_suspend, img_spdif_out_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static struct platform_driver img_spdif_out_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		.name = "img-spdif-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		.of_match_table = img_spdif_out_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		.pm = &img_spdif_out_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.probe = img_spdif_out_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	.remove = img_spdif_out_dev_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) module_platform_driver(img_spdif_out_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_DESCRIPTION("IMG SPDIF Output driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MODULE_LICENSE("GPL v2");