^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMG SPDIF input controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Damien Horsley <Damien.Horsley@imgtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMG_SPDIF_IN_RX_FIFO_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMG_SPDIF_IN_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMG_SPDIF_IN_CTL_LOCKLO_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMG_SPDIF_IN_CTL_LOCKLO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMG_SPDIF_IN_CTL_LOCKHI_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMG_SPDIF_IN_CTL_LOCKHI_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMG_SPDIF_IN_CTL_TRK_MASK 0xff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMG_SPDIF_IN_CTL_TRK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMG_SPDIF_IN_CTL_SRD_MASK 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMG_SPDIF_IN_CTL_SRD_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMG_SPDIF_IN_CTL_SRT_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMG_SPDIF_IN_STATUS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMG_SPDIF_IN_STATUS_SAM_MASK 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMG_SPDIF_IN_STATUS_SAM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMG_SPDIF_IN_STATUS_LOCK_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMG_SPDIF_IN_STATUS_LOCK_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMG_SPDIF_IN_CLKGEN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMG_SPDIF_IN_CLKGEN_NOM_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMG_SPDIF_IN_CLKGEN_NOM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMG_SPDIF_IN_CLKGEN_HLD_MASK 0x3ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMG_SPDIF_IN_CLKGEN_HLD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMG_SPDIF_IN_CSL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMG_SPDIF_IN_CSH 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMG_SPDIF_IN_CSH_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMG_SPDIF_IN_CSH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMG_SPDIF_IN_SOFT_RESET 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMG_SPDIF_IN_SOFT_RESET_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMG_SPDIF_IN_ACLKGEN_START 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMG_SPDIF_IN_ACLKGEN_NOM_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMG_SPDIF_IN_ACLKGEN_NOM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMG_SPDIF_IN_ACLKGEN_HLD_MASK 0xffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMG_SPDIF_IN_ACLKGEN_HLD_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMG_SPDIF_IN_ACLKGEN_TRK_MASK 0xff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMG_SPDIF_IN_NUM_ACLKGEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct img_spdif_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *clk_sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct snd_dmaengine_dai_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int trk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool multi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int lock_acquire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int lock_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int single_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int multi_freqs[IMG_SPDIF_IN_NUM_ACLKGEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 suspend_clkgen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 suspend_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Write-only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int aclkgen_regs[IMG_SPDIF_IN_NUM_ACLKGEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int img_spdif_in_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct img_spdif_in *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk_disable_unprepare(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int img_spdif_in_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct img_spdif_in *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = clk_prepare_enable(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(dev, "Unable to enable sys clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void img_spdif_in_writel(struct img_spdif_in *spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(val, spdif->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline u32 img_spdif_in_readl(struct img_spdif_in *spdif, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return readl(spdif->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void img_spdif_in_aclkgen_writel(struct img_spdif_in *spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) img_spdif_in_writel(spdif, spdif->aclkgen_regs[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) IMG_SPDIF_IN_ACLKGEN_START + (index * 0x4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int img_spdif_in_check_max_rate(struct img_spdif_in *spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int sample_rate, unsigned long *actual_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long min_freq, freq_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Clock rate must be at least 24x the bit rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) min_freq = sample_rate * 2 * 32 * 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) freq_t = clk_get_rate(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (freq_t < min_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *actual_freq = freq_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int img_spdif_in_do_clkgen_calc(unsigned int rate, unsigned int *pnom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int *phld, unsigned long clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int ori, nom, hld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Calculate oversampling ratio, nominal phase increment and hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * increment for the given rate / frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ori = clk_rate / (rate * 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!ori)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) nom = (4096 / ori) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hld = 4096 - (--nom * (ori - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) while (hld < 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *pnom = nom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *phld = hld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int img_spdif_in_do_clkgen_single(struct img_spdif_in *spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int nom, hld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long flags, clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = img_spdif_in_check_max_rate(spdif, rate, &clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = img_spdif_in_do_clkgen_calc(rate, &nom, &hld, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg = (nom << IMG_SPDIF_IN_CLKGEN_NOM_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IMG_SPDIF_IN_CLKGEN_NOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg |= (hld << IMG_SPDIF_IN_CLKGEN_HLD_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IMG_SPDIF_IN_CLKGEN_HLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (spdif->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CLKGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spdif->single_freq = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int img_spdif_in_do_clkgen_multi(struct img_spdif_in *spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int multi_freqs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int nom, hld, rate, max_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long flags, clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 reg, trk_reg, temp_regs[IMG_SPDIF_IN_NUM_ACLKGEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (multi_freqs[i] > max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) max_rate = multi_freqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = img_spdif_in_check_max_rate(spdif, max_rate, &clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rate = multi_freqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = img_spdif_in_do_clkgen_calc(rate, &nom, &hld, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg = (nom << IMG_SPDIF_IN_ACLKGEN_NOM_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMG_SPDIF_IN_ACLKGEN_NOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg |= (hld << IMG_SPDIF_IN_ACLKGEN_HLD_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMG_SPDIF_IN_ACLKGEN_HLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) temp_regs[i] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (spdif->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) trk_reg = spdif->trk << IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spdif->aclkgen_regs[i] = temp_regs[i] | trk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) img_spdif_in_aclkgen_writel(spdif, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spdif->multi_freq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spdif->multi_freqs[0] = multi_freqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) spdif->multi_freqs[1] = multi_freqs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) spdif->multi_freqs[2] = multi_freqs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) spdif->multi_freqs[3] = multi_freqs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int img_spdif_in_iec958_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int img_spdif_in_get_status_mask(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ucontrol->value.iec958.status[4] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int img_spdif_in_get_status(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ucontrol->value.iec958.status[0] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ucontrol->value.iec958.status[4] = (reg & IMG_SPDIF_IN_CSH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) >> IMG_SPDIF_IN_CSH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int img_spdif_in_info_multi_freq(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uinfo->count = IMG_SPDIF_IN_NUM_ACLKGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) uinfo->value.integer.max = LONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int img_spdif_in_get_multi_freq(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (spdif->multi_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ucontrol->value.integer.value[0] = spdif->multi_freqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ucontrol->value.integer.value[1] = spdif->multi_freqs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ucontrol->value.integer.value[2] = spdif->multi_freqs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ucontrol->value.integer.value[3] = spdif->multi_freqs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ucontrol->value.integer.value[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ucontrol->value.integer.value[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ucontrol->value.integer.value[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ucontrol->value.integer.value[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int img_spdif_in_set_multi_freq(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int multi_freqs[IMG_SPDIF_IN_NUM_ACLKGEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bool multi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if ((ucontrol->value.integer.value[0] == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (ucontrol->value.integer.value[1] == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (ucontrol->value.integer.value[2] == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (ucontrol->value.integer.value[3] == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) multi_freq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) multi_freqs[0] = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) multi_freqs[1] = ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) multi_freqs[2] = ucontrol->value.integer.value[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) multi_freqs[3] = ucontrol->value.integer.value[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) multi_freq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (multi_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return img_spdif_in_do_clkgen_multi(spdif, multi_freqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (spdif->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spdif->multi_freq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int img_spdif_in_info_lock_freq(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uinfo->value.integer.max = LONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int img_spdif_in_get_lock_freq(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct snd_ctl_elem_value *uc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (reg & IMG_SPDIF_IN_STATUS_LOCK_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (spdif->multi_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) i = ((reg & IMG_SPDIF_IN_STATUS_SAM_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) IMG_SPDIF_IN_STATUS_SAM_SHIFT) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) uc->value.integer.value[0] = spdif->multi_freqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uc->value.integer.value[0] = spdif->single_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uc->value.integer.value[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int img_spdif_in_info_trk(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int img_spdif_in_get_trk(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ucontrol->value.integer.value[0] = spdif->trk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int img_spdif_in_set_trk(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (spdif->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spdif->trk = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) reg &= ~IMG_SPDIF_IN_CTL_TRK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) reg |= spdif->trk << IMG_SPDIF_IN_CTL_TRK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spdif->aclkgen_regs[i] = (spdif->aclkgen_regs[i] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ~IMG_SPDIF_IN_ACLKGEN_TRK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) (spdif->trk << IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) img_spdif_in_aclkgen_writel(spdif, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int img_spdif_in_info_lock(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uinfo->value.integer.min = -128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uinfo->value.integer.max = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int img_spdif_in_get_lock_acquire(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ucontrol->value.integer.value[0] = spdif->lock_acquire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int img_spdif_in_set_lock_acquire(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (spdif->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spdif->lock_acquire = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) reg &= ~IMG_SPDIF_IN_CTL_LOCKHI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) reg |= (spdif->lock_acquire << IMG_SPDIF_IN_CTL_LOCKHI_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) IMG_SPDIF_IN_CTL_LOCKHI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int img_spdif_in_get_lock_release(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ucontrol->value.integer.value[0] = spdif->lock_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int img_spdif_in_set_lock_release(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (spdif->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) spdif->lock_release = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) reg &= ~IMG_SPDIF_IN_CTL_LOCKLO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) reg |= (spdif->lock_release << IMG_SPDIF_IN_CTL_LOCKLO_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) IMG_SPDIF_IN_CTL_LOCKLO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct snd_kcontrol_new img_spdif_in_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .info = img_spdif_in_iec958_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .get = img_spdif_in_get_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .info = img_spdif_in_iec958_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .get = img_spdif_in_get_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = "SPDIF In Multi Frequency Acquire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .info = img_spdif_in_info_multi_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .get = img_spdif_in_get_multi_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .put = img_spdif_in_set_multi_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .name = "SPDIF In Lock Frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .info = img_spdif_in_info_lock_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .get = img_spdif_in_get_lock_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "SPDIF In Lock TRK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .info = img_spdif_in_info_trk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .get = img_spdif_in_get_trk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .put = img_spdif_in_set_trk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "SPDIF In Lock Acquire Threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .info = img_spdif_in_info_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .get = img_spdif_in_get_lock_acquire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .put = img_spdif_in_set_lock_acquire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "SPDIF In Lock Release Threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .info = img_spdif_in_info_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .get = img_spdif_in_get_lock_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .put = img_spdif_in_set_lock_release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int img_spdif_in_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (spdif->multi_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) reg &= ~IMG_SPDIF_IN_CTL_SRD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) reg |= (1UL << IMG_SPDIF_IN_CTL_SRD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) reg |= IMG_SPDIF_IN_CTL_SRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) spdif->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) reg &= ~IMG_SPDIF_IN_CTL_SRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spdif->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int img_spdif_in_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned int rate, channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) snd_pcm_format_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (format != SNDRV_PCM_FORMAT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (channels != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return img_spdif_in_do_clkgen_single(spdif, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct snd_soc_dai_ops img_spdif_in_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .trigger = img_spdif_in_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .hw_params = img_spdif_in_hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int img_spdif_in_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) snd_soc_dai_init_dma_data(dai, NULL, &spdif->dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) snd_soc_add_dai_controls(dai, img_spdif_in_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ARRAY_SIZE(img_spdif_in_controls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct snd_soc_dai_driver img_spdif_in_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .probe = img_spdif_in_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .formats = SNDRV_PCM_FMTBIT_S32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .ops = &img_spdif_in_dai_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct snd_soc_component_driver img_spdif_in_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .name = "img-spdif-in"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int img_spdif_in_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct img_spdif_in *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) platform_set_drvdata(pdev, spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spdif->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spdif->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) spdif->clk_sys = devm_clk_get(dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (IS_ERR(spdif->clk_sys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (PTR_ERR(spdif->clk_sys) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(dev, "Failed to acquire clock 'sys'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return PTR_ERR(spdif->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = img_spdif_in_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (PTR_ERR(rst) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_dbg(dev, "No top level reset found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) img_spdif_in_writel(spdif, IMG_SPDIF_IN_SOFT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) IMG_SPDIF_IN_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) img_spdif_in_writel(spdif, 0, IMG_SPDIF_IN_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) spin_lock_init(&spdif->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spdif->dma_data.addr = res->start + IMG_SPDIF_IN_RX_FIFO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) spdif->dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) spdif->dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) spdif->trk = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spdif->lock_acquire = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) spdif->lock_release = -128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) reg = (spdif->lock_acquire << IMG_SPDIF_IN_CTL_LOCKHI_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) IMG_SPDIF_IN_CTL_LOCKHI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) reg |= (spdif->lock_release << IMG_SPDIF_IN_CTL_LOCKLO_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) IMG_SPDIF_IN_CTL_LOCKLO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) reg |= (spdif->trk << IMG_SPDIF_IN_CTL_TRK_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) IMG_SPDIF_IN_CTL_TRK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &img_spdif_in_component, &img_spdif_in_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) err_pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) img_spdif_in_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int img_spdif_in_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) img_spdif_in_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int img_spdif_in_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct img_spdif_in *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = img_spdif_in_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) spdif->suspend_clkgen = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CLKGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) spdif->suspend_ctl = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) img_spdif_in_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int img_spdif_in_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct img_spdif_in *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = img_spdif_in_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) img_spdif_in_aclkgen_writel(spdif, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) img_spdif_in_writel(spdif, spdif->suspend_clkgen, IMG_SPDIF_IN_CLKGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) img_spdif_in_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) img_spdif_in_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct of_device_id img_spdif_in_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) { .compatible = "img,spdif-in" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MODULE_DEVICE_TABLE(of, img_spdif_in_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const struct dev_pm_ops img_spdif_in_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SET_RUNTIME_PM_OPS(img_spdif_in_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) img_spdif_in_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) SET_SYSTEM_SLEEP_PM_OPS(img_spdif_in_suspend, img_spdif_in_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct platform_driver img_spdif_in_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "img-spdif-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .of_match_table = img_spdif_in_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .pm = &img_spdif_in_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .probe = img_spdif_in_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .remove = img_spdif_in_dev_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) module_platform_driver(img_spdif_in_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MODULE_DESCRIPTION("IMG SPDIF Input driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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