^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMG I2S output controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Damien Horsley <Damien.Horsley@imgtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMG_I2S_OUT_TX_FIFO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMG_I2S_OUT_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMG_I2S_OUT_CTL_DATA_EN_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK 0xffe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMG_I2S_OUT_CTL_FRM_SIZE_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMG_I2S_OUT_CTL_MASTER_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMG_I2S_OUT_CTL_CLK_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMG_I2S_OUT_CTL_CLK_EN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMG_I2S_OUT_CTL_BCLK_POL_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMG_I2S_OUT_CTL_ME_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMG_I2S_OUT_CH_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMG_I2S_OUT_CHAN_CTL_CH_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMG_I2S_OUT_CHAN_CTL_LT_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMG_I2S_OUT_CHAN_CTL_FMT_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMG_I2S_OUT_CHAN_CTL_JUST_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMG_I2S_OUT_CHAN_CTL_CLKT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMG_I2S_OUT_CHAN_CTL_ME_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMG_I2S_OUT_CH_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct img_i2s_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *clk_sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct snd_dmaengine_dai_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int max_i2s_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *channel_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bool force_clk_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int active_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct snd_soc_dai_driver dai_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 suspend_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 *suspend_ch_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int img_i2s_out_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct img_i2s_out *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_disable_unprepare(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clk_disable_unprepare(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int img_i2s_out_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct img_i2s_out *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = clk_prepare_enable(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = clk_prepare_enable(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_disable_unprepare(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline void img_i2s_out_writel(struct img_i2s_out *i2s, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(val, i2s->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline u32 img_i2s_out_readl(struct img_i2s_out *i2s, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return readl(i2s->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline void img_i2s_out_ch_writel(struct img_i2s_out *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 chan, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline u32 img_i2s_out_ch_readl(struct img_i2s_out *i2s, u32 chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return readl(i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline void img_i2s_out_ch_disable(struct img_i2s_out *i2s, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg &= ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void img_i2s_out_ch_enable(struct img_i2s_out *i2s, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg |= IMG_I2S_OUT_CHAN_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void img_i2s_out_disable(struct img_i2s_out *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg &= ~IMG_I2S_OUT_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline void img_i2s_out_enable(struct img_i2s_out *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) reg |= IMG_I2S_OUT_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void img_i2s_out_reset(struct img_i2s_out *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 core_ctl, chan_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) core_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ~IMG_I2S_OUT_CTL_ME_MASK &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ~IMG_I2S_OUT_CTL_DATA_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!i2s->force_clk_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) core_ctl &= ~IMG_I2S_OUT_CTL_CLK_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) chan_ctl = img_i2s_out_ch_readl(i2s, 0, IMG_I2S_OUT_CH_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reset_control_assert(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reset_control_deassert(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) for (i = 0; i < i2s->max_i2s_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) img_i2s_out_ch_writel(i2s, i, chan_ctl, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) img_i2s_out_ch_enable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) img_i2s_out_writel(i2s, core_ctl, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) img_i2s_out_enable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int img_i2s_out_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!i2s->force_clk_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg |= IMG_I2S_OUT_CTL_DATA_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) img_i2s_out_reset(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int img_i2s_out_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int channels, i2s_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 reg, control_mask, control_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) snd_pcm_format_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) i2s_channels = channels / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (format != SNDRV_PCM_FORMAT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if ((channels < 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (channels > (i2s->max_i2s_chan * 2)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (channels % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pre_div_a = clk_round_rate(i2s->clk_ref, rate * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (pre_div_a < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return pre_div_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pre_div_b = clk_round_rate(i2s->clk_ref, rate * 384);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (pre_div_b < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return pre_div_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) diff_a = abs((pre_div_a / 256) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) diff_b = abs((pre_div_b / 384) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* If diffs are equal, use lower clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (diff_a > diff_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk_set_rate(i2s->clk_ref, pre_div_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk_set_rate(i2s->clk_ref, pre_div_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Another driver (eg alsa machine driver) may have rejected the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * change. Get the current rate and set the register bit according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * the new minimum diff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_rate = clk_get_rate(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) diff_a = abs((clk_rate / 256) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) diff_b = abs((clk_rate / 384) - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (diff_a > diff_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) control_set |= IMG_I2S_OUT_CTL_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) control_set |= ((i2s_channels - 1) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) control_mask = IMG_I2S_OUT_CTL_CLK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) img_i2s_out_disable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reg = (reg & ~control_mask) | control_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) for (i = 0; i < i2s_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) img_i2s_out_ch_enable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (; i < i2s->max_i2s_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) img_i2s_out_ch_disable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) img_i2s_out_enable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) i2s->active_channels = i2s_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int img_i2s_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bool force_clk_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 chan_control_mask, control_mask, chan_control_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 reg, control_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) force_clk_active = ((fmt & SND_SOC_DAIFMT_CLOCK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SND_SOC_DAIFMT_CONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (force_clk_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) control_set |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) control_set |= IMG_I2S_OUT_CTL_MASTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) chan_control_set |= IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) control_mask = IMG_I2S_OUT_CTL_CLK_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) IMG_I2S_OUT_CTL_MASTER_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) IMG_I2S_OUT_CTL_BCLK_POL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) chan_control_mask = IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = pm_runtime_get_sync(i2s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pm_runtime_put_noidle(i2s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) img_i2s_out_disable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg = (reg & ~control_mask) | control_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) img_i2s_out_ch_disable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg = (reg & ~chan_control_mask) | chan_control_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) img_i2s_out_ch_enable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) img_i2s_out_enable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pm_runtime_put(i2s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) i2s->force_clk_active = force_clk_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct snd_soc_dai_ops img_i2s_out_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .trigger = img_i2s_out_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .hw_params = img_i2s_out_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .set_fmt = img_i2s_out_set_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int img_i2s_out_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) snd_soc_dai_init_dma_data(dai, &i2s->dma_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct snd_soc_component_driver img_i2s_out_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "img-i2s-out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int img_i2s_out_dma_prepare_slave_config(struct snd_pcm_substream *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int i2s_channels = params_channels(params) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct snd_soc_pcm_runtime *rtd = st->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = snd_hwparams_to_dma_slave_config(st, params, sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) sc->dst_addr = dma_data->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sc->dst_addr_width = dma_data->addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) sc->dst_maxburst = 4 * i2s_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct snd_dmaengine_pcm_config img_i2s_out_dma_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .prepare_slave_config = img_i2s_out_dma_prepare_slave_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int img_i2s_out_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct img_i2s_out *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int max_i2s_chan_pow_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) platform_set_drvdata(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) i2s->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i2s->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &i2s->max_i2s_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&pdev->dev, "No img,i2s-channels property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (IS_ERR(i2s->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (PTR_ERR(i2s->rst) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(&pdev->dev, "No top level reset found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return PTR_ERR(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) i2s->clk_sys = devm_clk_get(&pdev->dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (IS_ERR(i2s->clk_sys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (PTR_ERR(i2s->clk_sys) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(dev, "Failed to acquire clock 'sys'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return PTR_ERR(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) i2s->clk_ref = devm_clk_get(&pdev->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (IS_ERR(i2s->clk_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (PTR_ERR(i2s->clk_ref) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(dev, "Failed to acquire clock 'ref'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return PTR_ERR(i2s->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i2s->suspend_ch_ctl = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!i2s->suspend_ch_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = img_i2s_out_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) reg = IMG_I2S_OUT_CTL_FRM_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) reg = IMG_I2S_OUT_CHAN_CTL_JUST_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) IMG_I2S_OUT_CHAN_CTL_LT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) IMG_I2S_OUT_CHAN_CTL_CH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (8 << IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (i = 0; i < i2s->max_i2s_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) img_i2s_out_reset(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i2s->active_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) i2s->dma_data.addr = res->start + IMG_I2S_OUT_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) i2s->dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) i2s->dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) i2s->dai_driver.probe = img_i2s_out_dai_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) i2s->dai_driver.playback.channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) i2s->dai_driver.playback.channels_max = i2s->max_i2s_chan * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) i2s->dai_driver.playback.rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) i2s->dai_driver.playback.formats = SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) i2s->dai_driver.ops = &img_i2s_out_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &img_i2s_out_component, &i2s->dai_driver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &img_i2s_out_dma_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) img_i2s_out_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int img_i2s_out_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) img_i2s_out_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int img_i2s_out_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct img_i2s_out *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = img_i2s_out_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i2s->suspend_ch_ctl[i] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) i2s->suspend_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) img_i2s_out_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int img_i2s_out_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct img_i2s_out *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = img_i2s_out_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) reg = i2s->suspend_ch_ctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) img_i2s_out_writel(i2s, i2s->suspend_ctl, IMG_I2S_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) img_i2s_out_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct of_device_id img_i2s_out_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { .compatible = "img,i2s-out" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_DEVICE_TABLE(of, img_i2s_out_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const struct dev_pm_ops img_i2s_out_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) SET_RUNTIME_PM_OPS(img_i2s_out_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) img_i2s_out_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) SET_SYSTEM_SLEEP_PM_OPS(img_i2s_out_suspend, img_i2s_out_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct platform_driver img_i2s_out_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .name = "img-i2s-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .of_match_table = img_i2s_out_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .pm = &img_i2s_out_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .probe = img_i2s_out_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .remove = img_i2s_out_dev_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) module_platform_driver(img_i2s_out_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_DESCRIPTION("IMG I2S Output Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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