^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMG I2S input controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Damien Horsley <Damien.Horsley@imgtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMG_I2S_IN_RX_FIFO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMG_I2S_IN_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK 0xfffffffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMG_I2S_IN_CTL_16PACK_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMG_I2S_IN_CTL_ME_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMG_I2S_IN_CH_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMG_I2S_IN_CH_CTL_CCDEL_MASK 0x38000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMG_I2S_IN_CH_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct img_i2s_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk_sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct snd_dmaengine_dai_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int max_i2s_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *channel_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int active_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct snd_soc_dai_driver dai_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 suspend_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 *suspend_ch_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int img_i2s_in_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct img_i2s_in *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_disable_unprepare(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int img_i2s_in_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct img_i2s_in *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = clk_prepare_enable(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(dev, "Unable to enable sys clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(val, i2s->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return readl(i2s->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg &= ~IMG_I2S_IN_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg |= IMG_I2S_IN_CTL_ME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; i < i2s->active_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) img_i2s_in_enable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) img_i2s_in_disable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int sample_rate, unsigned int frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int *bclk_filter_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int *bclk_filter_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int bclk_freq, cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bclk_freq = sample_rate * frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cur_freq = clk_get_rate(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (cur_freq >= bclk_freq * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *bclk_filter_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *bclk_filter_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } else if (cur_freq >= bclk_freq * 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *bclk_filter_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *bclk_filter_value = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else if (cur_freq >= bclk_freq * 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *bclk_filter_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *bclk_filter_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(i2s->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "Sys clock rate %u insufficient for sample rate %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cur_freq, sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int rate, channels, i2s_channels, frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int bclk_filter_enable, bclk_filter_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 reg, control_mask, chan_control_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 control_set = 0, chan_control_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snd_pcm_format_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) i2s_channels = channels / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) frame_size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) frame_size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) frame_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((channels < 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (channels > (i2s->max_i2s_chan * 2)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (channels % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = img_i2s_in_check_rate(i2s, rate, frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &bclk_filter_enable, &bclk_filter_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (bclk_filter_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (bclk_filter_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IMG_I2S_IN_CH_CTL_FEN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IMG_I2S_IN_CH_CTL_FMODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IMG_I2S_IN_CH_CTL_SW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) IMG_I2S_IN_CH_CTL_FW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IMG_I2S_IN_CH_CTL_PACKH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reg = (reg & ~control_mask) | control_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) img_i2s_in_ch_disable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reg = (reg & ~chan_control_mask) | chan_control_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) i2s->active_channels = i2s_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) img_i2s_in_flush(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) img_i2s_in_ch_enable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = pm_runtime_get_sync(i2s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pm_runtime_put_noidle(i2s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) img_i2s_in_ch_disable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * BLKP and LRD must be set during separate register writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reg = (reg & ~chan_control_mask) | chan_control_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for (i = 0; i < i2s->active_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) img_i2s_in_ch_enable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pm_runtime_put(i2s->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .trigger = img_i2s_in_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .hw_params = img_i2s_in_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .set_fmt = img_i2s_in_set_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct snd_soc_component_driver img_i2s_in_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .name = "img-i2s-in"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int i2s_channels = params_channels(params) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct snd_soc_pcm_runtime *rtd = st->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = snd_hwparams_to_dma_slave_config(st, params, sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sc->src_addr = dma_data->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sc->src_addr_width = dma_data->addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) sc->src_maxburst = 4 * i2s_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .prepare_slave_config = img_i2s_in_dma_prepare_slave_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int img_i2s_in_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct img_i2s_in *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int max_i2s_chan_pow_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) platform_set_drvdata(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) i2s->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) i2s->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &i2s->max_i2s_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "No img,i2s-channels property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) i2s->clk_sys = devm_clk_get(dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (IS_ERR(i2s->clk_sys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (PTR_ERR(i2s->clk_sys) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(dev, "Failed to acquire clock 'sys'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return PTR_ERR(i2s->clk_sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = img_i2s_in_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = pm_runtime_resume_and_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) i2s->active_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) i2s->dma_data.addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) i2s->dai_driver.probe = img_i2s_in_dai_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) i2s->dai_driver.capture.channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i2s->dai_driver.ops = &img_i2s_in_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rst = devm_reset_control_get_exclusive(dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (PTR_ERR(rst) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_dbg(dev, "No top level reset found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) img_i2s_in_disable(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < i2s->max_i2s_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) img_i2s_in_ch_disable(i2s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = 0; i < i2s->max_i2s_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) img_i2s_in_ch_writel(i2s, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) IMG_I2S_IN_CH_CTL_JUST_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i2s->suspend_ch_ctl = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!i2s->suspend_ch_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &i2s->dai_driver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) img_i2s_in_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int img_i2s_in_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) img_i2s_in_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int img_i2s_in_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct img_i2s_in *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = img_i2s_in_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) i2s->suspend_ch_ctl[i] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) i2s->suspend_ctl = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) img_i2s_in_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int img_i2s_in_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct img_i2s_in *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = img_i2s_in_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (i = 0; i < i2s->max_i2s_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) reg = i2s->suspend_ch_ctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) img_i2s_in_writel(i2s, i2s->suspend_ctl, IMG_I2S_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) img_i2s_in_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct of_device_id img_i2s_in_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { .compatible = "img,i2s-in" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct dev_pm_ops img_i2s_in_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SET_RUNTIME_PM_OPS(img_i2s_in_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) img_i2s_in_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SET_SYSTEM_SLEEP_PM_OPS(img_i2s_in_suspend, img_i2s_in_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct platform_driver img_i2s_in_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "img-i2s-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .of_match_table = img_i2s_in_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .pm = &img_i2s_in_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .probe = img_i2s_in_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .remove = img_i2s_in_dev_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) module_platform_driver(img_i2s_in_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_DESCRIPTION("IMG I2S Input Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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