Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/sound/soc/hisilicon/hi6210-i2s.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Linaro, Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Andy Green <andy.green@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Note at least on 6220, S2 == BT, S1 == Digital FM Radio IF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _HI6210_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _HI6210_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define HII2S_SW_RST_N				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HII2S_SW_RST_N__SW_RST_N					BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) enum hi6210_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	HII2S_BITS_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	HII2S_BITS_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	HII2S_BITS_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	HII2S_BITS_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HII2S_IF_CLK_EN_CFG			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN				BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN				BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN				BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN				BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN				BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN				BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN				BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN				BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN				BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN				BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN				BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN				BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN				BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN					BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN					BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN				BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN				BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN				BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN				BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HII2S_DIG_FILTER_CLK_EN_CFG		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN			BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN			BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN			BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN			BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN			BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN			BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN			BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HII2S_FS_CFG				0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HII2S_FS_CFG__FS_S2_SHIFT					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HII2S_FS_CFG__FS_S2_MASK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HII2S_FS_CFG__FS_S1_SHIFT					24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HII2S_FS_CFG__FS_S1_MASK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HII2S_FS_CFG__FS_ADCLR_SHIFT					20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HII2S_FS_CFG__FS_ADCLR_MASK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HII2S_FS_CFG__FS_DACLR_SHIFT					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HII2S_FS_CFG__FS_DACLR_MASK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HII2S_FS_CFG__FS_ST_DL_R_SHIFT					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HII2S_FS_CFG__FS_ST_DL_R_MASK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HII2S_FS_CFG__FS_ST_DL_L_SHIFT					4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HII2S_FS_CFG__FS_ST_DL_L_MASK					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HII2S_FS_CFG__FS_VOICE_DLINK_MASK				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) enum hi6210_i2s_rates {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	HII2S_FS_RATE_8KHZ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	HII2S_FS_RATE_16KHZ = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	HII2S_FS_RATE_32KHZ = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	HII2S_FS_RATE_48KHZ = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	HII2S_FS_RATE_96KHZ = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	HII2S_FS_RATE_192KHZ = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HII2S_I2S_CFG				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HII2S_I2S_CFG__S2_IF_TX_EN					BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HII2S_I2S_CFG__S2_IF_RX_EN					BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HII2S_I2S_CFG__S2_FRAME_MODE					BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HII2S_I2S_CFG__S2_MST_SLV					BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HII2S_I2S_CFG__S2_LRCK_MODE					BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HII2S_I2S_CFG__S2_CHNNL_MODE					BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HII2S_I2S_CFG__S2_TX_CLK_SEL					BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HII2S_I2S_CFG__S2_RX_CLK_SEL					BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT				BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HII2S_I2S_CFG__S2_FUNC_MODE_MASK				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HII2S_I2S_CFG__S1_IF_TX_EN					BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HII2S_I2S_CFG__S1_IF_RX_EN					BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HII2S_I2S_CFG__S1_FRAME_MODE					BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HII2S_I2S_CFG__S1_MST_SLV					BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HII2S_I2S_CFG__S1_LRCK_MODE					BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HII2S_I2S_CFG__S1_CHNNL_MODE					BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HII2S_I2S_CFG__S1_TX_CLK_SEL					BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HII2S_I2S_CFG__S1_RX_CLK_SEL					BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT				BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HII2S_I2S_CFG__S1_FUNC_MODE_MASK				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum hi6210_i2s_formats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	HII2S_FORMAT_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	HII2S_FORMAT_PCM_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	HII2S_FORMAT_PCM_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	HII2S_FORMAT_LEFT_JUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	HII2S_FORMAT_RIGHT_JUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HII2S_DIG_FILTER_MODULE_CFG		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE		BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE		BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE		BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE		BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum hi6210_gains {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	HII2S_GAIN_100PC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	HII2S_GAIN_50PC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	HII2S_GAIN_25PC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HII2S_MUX_TOP_MODULE_CFG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY				BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) enum hi6210_s2_src_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	HII2S_S2_SRC_MODE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	HII2S_S2_SRC_MODE_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	HII2S_S2_SRC_MODE_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	HII2S_S2_SRC_MODE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum hi6210_voice_dlink_src_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	HII2S_VOICE_DL_SRC_MODE_12 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	HII2S_VOICE_DL_SRC_MODE_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	HII2S_VOICE_DL_SRC_MODE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	HII2S_VOICE_DL_SRC_MODE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HII2S_ADC_PGA_CFG			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HII2S_S1_INPUT_PGA_CFG			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HII2S_S2_INPUT_PGA_CFG			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HII2S_ST_DL_PGA_CFG			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HII2S_VOICE_SIDETONE_DLINK_PGA_CFG	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HII2S_APB_AFIFO_CFG_1			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HII2S_APB_AFIFO_CFG_2			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HII2S_ST_DL_FIFO_TH_CFG			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HII2S_STEREO_UPLINK_FIFO_TH_CFG		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HII2S_VOICE_UPLINK_FIFO_TH_CFG		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HII2S_CODEC_IRQ_MASK			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HII2S_CODEC_IRQ				0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HII2S_DACL_AGC_CFG_1			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HII2S_DACL_AGC_CFG_2			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HII2S_DACR_AGC_CFG_1			0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HII2S_DACR_AGC_CFG_2			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HII2S_DMIC_SIF_CFG			0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HII2S_MISC_CFG				0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL				BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL				BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL				BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL				BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HII2S_MISC_CFG__S3_DIN_TEST_SEL					BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL				BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL				BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HII2S_MISC_CFG__ST_DL_TEST_SEL					BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL				BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HII2S_MISC_CFG__S2_DOUT_TEST_SEL				BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HII2S_MISC_CFG__S1_DOUT_TEST_SEL				BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL				BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HII2S_S2_SRC_CFG			0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HII2S_MEM_CFG				0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HII2S_THIRDMD_PCM_PGA_CFG		0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HII2S_THIRD_MODEM_FIFO_TH		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT	0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT	0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT	0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HII2S_ANTI_FREQ_JITTER_EN		0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HII2S_CLK_SEL				0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* 0 = BT owns the i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HII2S_CLK_SEL__I2S_BT_FM_SEL					BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* 0 = internal source, 1 = ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HII2S_CLK_SEL__EXT_12_288MHZ_SEL				BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HII2S_THIRDMD_DLINK_CHANNEL		0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HII2S_THIRDMD_ULINK_CHANNEL		0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HII2S_VOICE_DLINK_CHANNEL		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* shovel data in here for playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define HII2S_ST_DL_CHANNEL			0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define HII2S_STEREO_UPLINK_CHANNEL		0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HII2S_VOICE_UPLINK_CHANNEL		0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif/* _HI6210_I2S_H */