^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Linaro, Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Andy Green <andy.green@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver only deals with S2 interface (BT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "hi6210-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct hi6210_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct reset_control *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *clk[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct snd_soc_dai_driver dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *sysctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) phys_addr_t base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct snd_dmaengine_dai_dma_data dma_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 channel_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 master:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 status:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC_PERIPH_CLKEN1 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC_PERIPH_CLKDIS1 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC_PERIPH_CLKEN3 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC_PERIPH_CLKDIS3 0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC_PERIPH_CLKEN12 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC_PERIPH_CLKDIS12 0x274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC_PERIPH_RSTEN1 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC_PERIPH_RSTDIS1 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC_PERIPH_RSTSTAT1 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC_PERIPH_RSTEN2 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC_PERIPH_RSTDIS2 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC_PERIPH_RSTSTAT2 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SOC_PMCTRL_BBPPLLALIAS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CLK_DACODEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CLK_I2S_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(val, i2s->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return readl(i2s->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* deassert reset on ABB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (val & BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (n = 0; n < i2s->clocks; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = clk_prepare_enable(i2s->clk[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto err_unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) goto err_unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* enable clock before frequency division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* enable codec working clock / == "codec bus clock" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* deassert reset on codec / interface clock / working clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* not interested in i2s irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* reset the stereo downlink fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val |= (BIT(5) | BIT(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val &= ~(BIT(5) | BIT(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* mux 11/12 = APB not i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* BT R ch 0 = mixer op of DACR ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* BT L ch = 1 = mux 7 = "mixer output of DACL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val |= HII2S_SW_RST_N__SW_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) err_unprepare_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clk_disable_unprepare(i2s->clk[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (n = 0; n < i2s->clocks; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk_disable_unprepare(i2s->clk[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spin_lock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* enable S2 TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val |= HII2S_I2S_CFG__S2_IF_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* disable S2 TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) spin_unlock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spin_lock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val |= HII2S_I2S_CFG__S2_IF_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_unlock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * We don't actually set the hardware until the hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * call, but we need to validate the user input here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) i2s->format = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SND_SOC_DAIFMT_CBS_CFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case SNDRV_PCM_FORMAT_U16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bits = HII2S_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case SNDRV_PCM_FORMAT_U24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bits = HII2S_BITS_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(cpu_dai->dev, "Bad format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rate = HII2S_FS_RATE_8KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rate = HII2S_FS_RATE_16KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rate = HII2S_FS_RATE_32KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rate = HII2S_FS_RATE_48KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rate = HII2S_FS_RATE_96KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rate = HII2S_FS_RATE_192KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!(params_channels(params))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(cpu_dai->dev, "Bad channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) switch (bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case HII2S_BITS_24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) i2s->bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dma_data->addr_width = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) i2s->bits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_data->addr_width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i2s->rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) i2s->channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) i2s->channel_length = i2s->channels * i2s->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val |= (BIT(19) | BIT(18) | BIT(17) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) i2s->master = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val |= HII2S_I2S_CFG__S2_MST_SLV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) i2s->master = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val &= ~HII2S_I2S_CFG__S2_MST_SLV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) fmt = HII2S_FORMAT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fmt = HII2S_FORMAT_LEFT_JUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) fmt = HII2S_FORMAT_RIGHT_JUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dma_data->maxburst = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (i2s->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) val |= HII2S_I2S_CFG__S2_FRAME_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* clear loopback, set signed type and word length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val |= signed_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!i2s->master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* set DAC and related units to correct rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val = hi6210_read_reg(i2s, HII2S_FS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hi6210_write_reg(i2s, HII2S_FS_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hi6210_i2s_rxctrl(cpu_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hi6210_i2s_txctrl(cpu_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hi6210_i2s_rxctrl(cpu_dai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hi6210_i2s_txctrl(cpu_dai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(cpu_dai->dev, "unknown cmd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .trigger = hi6210_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .hw_params = hi6210_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .set_fmt = hi6210_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .startup = hi6210_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .shutdown = hi6210_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .probe = hi6210_i2s_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) SNDRV_PCM_FMTBIT_U16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SNDRV_PCM_FMTBIT_U16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .ops = &hi6210_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "hi6210_i2s-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int hi6210_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct hi6210_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) i2s->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) spin_lock_init(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) i2s->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (IS_ERR(i2s->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return PTR_ERR(i2s->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) i2s->base_phys = (phys_addr_t)res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) i2s->dai = hi6210_i2s_dai_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_set_drvdata(dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "hisilicon,sysctrl-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (IS_ERR(i2s->sysctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return PTR_ERR(i2s->sysctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (IS_ERR(i2s->clk[CLK_DACODEC]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return PTR_ERR(i2s->clk[CLK_DACODEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) i2s->clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (IS_ERR(i2s->clk[CLK_I2S_BASE]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) i2s->clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = devm_snd_soc_register_component(dev, &hi6210_i2s_i2s_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &i2s->dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct of_device_id hi6210_i2s_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { .compatible = "hisilicon,hi6210-i2s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct platform_driver hi6210_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .probe = hi6210_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = "hi6210_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .of_match_table = hi6210_i2s_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) module_platform_driver(hi6210_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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