^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/sound/soc/hisilicon/hi3660-i2s.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * I2S IP driver for hi3660.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _HI3660_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _HI3660_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum hisi_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) HII2S_BITS_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) HII2S_BITS_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) HII2S_BITS_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) HII2S_BITS_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum hisi_i2s_rates {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) HII2S_FS_RATE_8KHZ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) HII2S_FS_RATE_16KHZ = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) HII2S_FS_RATE_32KHZ = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) HII2S_FS_RATE_48KHZ = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) HII2S_FS_RATE_96KHZ = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) HII2S_FS_RATE_192KHZ = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI_ASP_CFG_R_RST_CTRLEN_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI_ASP_CFG_R_RST_CTRLDIS_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HI_ASP_CFG_R_GATE_EN_REG 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HI_ASP_CFG_R_GATE_DIS_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI_ASP_CFG_R_GATE_CLKEN_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HI_ASP_CFG_R_GATE_CLKSTAT_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HI_ASP_CFG_R_GATE_CLKDIV_EN_REG 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HI_ASP_CFG_R_CLK1_DIV_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HI_ASP_CFG_R_CLK2_DIV_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HI_ASP_CFG_R_CLK3_DIV_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HI_ASP_CFG_R_CLK4_DIV_REG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HI_ASP_CFG_R_CLK5_DIV_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HI_ASP_CFG_R_CLK6_DIV_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HI_ASP_CFG_R_CLK_SEL_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HI_ASP_CFG_R_SEC_REG 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HI_ASP_SIO_VERSION_REG (0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HI_ASP_SIO_MODE_REG (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HI_ASP_SIO_INTSTATUS_REG (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI_ASP_SIO_INTCLR_REG (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HI_ASP_SIO_I2S_LEFT_XD_REG (0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HI_ASP_SIO_I2S_RIGHT_XD_REG (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HI_ASP_SIO_I2S_LEFT_RD_REG (0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HI_ASP_SIO_I2S_RIGHT_RD_REG (0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HI_ASP_SIO_CT_SET_REG (0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HI_ASP_SIO_CT_CLR_REG (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HI_ASP_SIO_RX_STA_REG (0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HI_ASP_SIO_TX_STA_REG (0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HI_ASP_SIO_DATA_WIDTH_SET_REG (0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HI_ASP_SIO_I2S_START_POS_REG (0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HI_ASP_SIO_I2S_POS_FLAG_REG (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HI_ASP_SIO_SIGNED_EXT_REG (0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HI_ASP_SIO_I2S_POS_MERGE_EN_REG (0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HI_ASP_SIO_INTMASK_REG (0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HI_ASP_SIO_I2S_DUAL_RX_CHN_REG (0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HI_ASP_SIO_I2S_DUAL_TX_CHN_REG (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HI_ASP_CFG_R_CLK_SEL_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HI_ASP_CFG_R_CLK_SEL 0x140010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HI_ASP_CFG_R_CLK1_DIV_SEL 0xbcdc9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HI_ASP_CFG_R_CLK6_DIV_SEL 0x00ff003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HI_ASP_CFG_SIO_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HI_ASP_SIO_MODE_SEL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HI_ASP_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HI_ASP_SIO_RX_ENABLE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HI_ASP_SIO_TX_ENABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HI_ASP_SIO_RX_FIFO_DISABLE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HI_ASP_SIO_TX_FIFO_DISABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HI_ASP_SIO_RX_DATA_MERGE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HI_ASP_SIO_TX_DATA_MERGE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HI_ASP_SIO_RX_FIFO_THRESHOLD (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HI_ASP_SIO_TX_FIFO_THRESHOLD (0xB << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HI_ASP_SIO_RX_FIFO_THRESHOLD_CLR (0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HI_ASP_SIO_TX_FIFO_THRESHOLD_CLR (0xF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HI_ASP_SIO_BURST (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum hisi_i2s_formats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) HII2S_FORMAT_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) HII2S_FORMAT_PCM_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) HII2S_FORMAT_PCM_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) HII2S_FORMAT_LEFT_JUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) HII2S_FORMAT_RIGHT_JUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif/* _HI3660_I2S_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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