^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/sound/soc/hisilicon/hi3660-i2s.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * I2S IP driver for hi3660.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "hi3660-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct hi3660_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct reset_control *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regulator *regu_asp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pinctrl_state *pin_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pinctrl_state *pin_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk *asp_subsys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct snd_soc_dai_driver dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *base_syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) phys_addr_t base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct snd_dmaengine_dai_dma_data dma_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void update_bits(struct hi3660_i2s *i2s, u32 ofs, u32 reset, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 val = readl(i2s->base + ofs) & ~reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel(val | set, i2s->base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void update_bits_syscon(struct hi3660_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 ofs, u32 reset, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val = readl(i2s->base_syscon + ofs) & ~reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(val | set, i2s->base_syscon + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int enable_format(struct hi3660_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) i2s->master = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0, HI_ASP_CFG_R_CLK_SEL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) i2s->master = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) HI_ASP_CFG_R_CLK_SEL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* deassert reset on sio_bt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) update_bits_syscon(i2s, HI_ASP_CFG_R_RST_CTRLDIS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0, BIT(2)|BIT(6)|BIT(8)|BIT(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* enable clk before frequency division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_EN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0, BIT(5)|BIT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* enable frequency division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_CLKDIV_EN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0, BIT(2)|BIT(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* select clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) HI_ASP_MASK, HI_ASP_CFG_R_CLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* select clk_div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) update_bits_syscon(i2s, HI_ASP_CFG_R_CLK1_DIV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) HI_ASP_MASK, HI_ASP_CFG_R_CLK1_DIV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) update_bits_syscon(i2s, HI_ASP_CFG_R_CLK4_DIV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) HI_ASP_MASK, HI_ASP_CFG_R_CLK4_DIV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) update_bits_syscon(i2s, HI_ASP_CFG_R_CLK6_DIV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) HI_ASP_MASK, HI_ASP_CFG_R_CLK6_DIV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* sio config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) update_bits(i2s, HI_ASP_SIO_MODE_REG, HI_ASP_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) update_bits(i2s, HI_ASP_SIO_DATA_WIDTH_SET_REG, HI_ASP_MASK, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) update_bits(i2s, HI_ASP_SIO_I2S_POS_MERGE_EN_REG, HI_ASP_MASK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) update_bits(i2s, HI_ASP_SIO_I2S_START_POS_REG, HI_ASP_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!IS_ERR_OR_NULL(i2s->asp_subsys_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk_disable_unprepare(i2s->asp_subsys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void txctrl(struct snd_soc_dai *cpu_dai, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) spin_lock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* enable SIO TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) HI_ASP_SIO_TX_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) HI_ASP_SIO_TX_DATA_MERGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) HI_ASP_SIO_TX_FIFO_THRESHOLD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) HI_ASP_SIO_RX_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) HI_ASP_SIO_RX_DATA_MERGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) HI_ASP_SIO_RX_FIFO_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* disable SIO TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spin_unlock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void rxctrl(struct snd_soc_dai *cpu_dai, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spin_lock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* enable SIO RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) HI_ASP_SIO_TX_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) HI_ASP_SIO_TX_DATA_MERGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HI_ASP_SIO_TX_FIFO_THRESHOLD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HI_ASP_SIO_RX_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) HI_ASP_SIO_RX_DATA_MERGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) HI_ASP_SIO_RX_FIFO_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* disable SIO RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_unlock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int set_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int set_format(struct snd_soc_dai *cpu_dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) i2s->format = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SND_SOC_DAIFMT_CBS_CFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enable_format(i2s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dma_data->maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dma_data->addr = i2s->base_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) HI_ASP_SIO_I2S_DUAL_TX_CHN_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dma_data->addr = i2s->base_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) HI_ASP_SIO_I2S_DUAL_RX_CHN_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case SNDRV_PCM_FORMAT_U16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) i2s->bits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dma_data->addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case SNDRV_PCM_FORMAT_U24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) i2s->bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dma_data->addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(cpu_dai->dev, "Bad format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rxctrl(cpu_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) txctrl(cpu_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rxctrl(cpu_dai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) txctrl(cpu_dai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(cpu_dai->dev, "unknown cmd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct hi3660_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct snd_soc_dai_ops dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .trigger = trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .hw_params = hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .set_fmt = set_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .set_sysclk = set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .startup = startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .shutdown = shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct snd_soc_dai_driver dai_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .name = "hi3660_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .probe = dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SNDRV_PCM_FMTBIT_U16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SNDRV_PCM_FMTBIT_U16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ops = &dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct snd_soc_component_driver component_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "hi3660_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct snd_pcm_hardware sound_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SNDRV_PCM_INFO_HALF_DUPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .period_bytes_min = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .period_bytes_max = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .periods_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .periods_max = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .buffer_bytes_max = SIZE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct snd_dmaengine_pcm_config dmaengine_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .pcm_hardware = &sound_hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .prealloc_buffer_size = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int hi3660_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct hi3660_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) i2s->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) spin_lock_init(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) i2s->base_phys = (phys_addr_t)res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) i2s->dai = dai_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_set_drvdata(&pdev->dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) i2s->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (IS_ERR(i2s->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_err(&pdev->dev, "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = PTR_ERR(i2s->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) i2s->base_syscon = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (IS_ERR(i2s->base_syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(&pdev->dev, "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = PTR_ERR(i2s->base_syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* i2s iomux config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) i2s->pctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (IS_ERR(i2s->pctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_err(dev, "could not get pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) i2s->pin_default = pinctrl_lookup_state(i2s->pctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (IS_ERR(i2s->pin_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "could not get default state (%li)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PTR_ERR(i2s->pin_default));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (pinctrl_select_state(i2s->pctrl, i2s->pin_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(dev, "could not set pins to default state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &dmaengine_pcm_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = snd_soc_register_component(&pdev->dev, &component_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &i2s->dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(&pdev->dev, "Failed to register dai\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int hi3660_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct hi3660_i2s *i2s = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_set_drvdata(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pinctrl_put(i2s->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct of_device_id dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .compatible = "hisilicon,hi3660-i2s-1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_DEVICE_TABLE(of, dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct platform_driver local_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .probe = hi3660_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .remove = hi3660_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "hi3660_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .of_match_table = dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) module_platform_driver(local_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DESCRIPTION("Hisilicon I2S driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_AUTHOR("Guangke Ji <j00209069@notesmail.huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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