Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // mx27vis-aic32x4.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright 2011 Vista Silicon S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Author: Javier Martin <javier.martin@vista-silicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_data/asoc-mx27vis.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/soc-dapm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "../codecs/tlv320aic32x4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "imx-ssi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "imx-audmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MX27VIS_AMP_GAIN	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MX27VIS_AMP_MUTE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static int mx27vis_amp_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static int mx27vis_amp_mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int mx27vis_amp_gain0_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int mx27vis_amp_gain1_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int mx27vis_amp_mutel_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int mx27vis_amp_muter_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int mx27vis_aic32x4_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			    struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	ret = snd_soc_dai_set_sysclk(codec_dai, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				     25000000, SND_SOC_CLOCK_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		pr_err("%s: failed setting codec sysclk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				SND_SOC_CLOCK_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct snd_soc_ops mx27vis_aic32x4_snd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.hw_params	= mx27vis_aic32x4_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int mx27vis_amp_set(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct soc_mixer_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		(struct soc_mixer_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int reg = mc->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int max = mc->max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (value > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	case MX27VIS_AMP_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		gpio_set_value(mx27vis_amp_gain0_gpio, value & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		gpio_set_value(mx27vis_amp_gain1_gpio, value >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		mx27vis_amp_gain = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	case MX27VIS_AMP_MUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		gpio_set_value(mx27vis_amp_mutel_gpio, value & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		gpio_set_value(mx27vis_amp_muter_gpio, value >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		mx27vis_amp_mute = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int mx27vis_amp_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct soc_mixer_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		(struct soc_mixer_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned int reg = mc->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case MX27VIS_AMP_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		ucontrol->value.integer.value[0] = mx27vis_amp_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case MX27VIS_AMP_MUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		ucontrol->value.integer.value[0] = mx27vis_amp_mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* From 6dB to 24dB in steps of 6dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const DECLARE_TLV_DB_SCALE(mx27vis_amp_tlv, 600, 600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct snd_kcontrol_new mx27vis_aic32x4_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	SOC_DAPM_PIN_SWITCH("External Mic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	SOC_SINGLE_EXT_TLV("LO Ext Boost", MX27VIS_AMP_GAIN, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		       mx27vis_amp_get, mx27vis_amp_set, mx27vis_amp_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	SOC_DOUBLE_EXT("LO Ext Mute Switch", MX27VIS_AMP_MUTE, 0, 1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		       mx27vis_amp_get, mx27vis_amp_set),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	SND_SOC_DAPM_MIC("External Mic", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{"Mic Bias", NULL, "External Mic"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{"IN1_R", NULL, "Mic Bias"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{"IN2_R", NULL, "Mic Bias"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{"IN3_R", NULL, "Mic Bias"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{"IN1_L", NULL, "Mic Bias"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{"IN2_L", NULL, "Mic Bias"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{"IN3_L", NULL, "Mic Bias"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SND_SOC_DAILINK_DEFS(hifi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	DAILINK_COMP_ARRAY(COMP_CPU("imx-ssi.0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic32x4.0-0018",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				      "tlv320aic32x4-hifi")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	DAILINK_COMP_ARRAY(COMP_PLATFORM("imx-ssi.0")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct snd_soc_dai_link mx27vis_aic32x4_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.name		= "tlv320aic32x4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.stream_name	= "TLV320AIC32X4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.dai_fmt	= SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_NB_NF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			  SND_SOC_DAIFMT_CBM_CFM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.ops		= &mx27vis_aic32x4_snd_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	SND_SOC_DAILINK_REG(hifi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct snd_soc_card mx27vis_aic32x4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.name		= "visstrim_m10-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.dai_link	= &mx27vis_aic32x4_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.num_links	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.controls	= mx27vis_aic32x4_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.num_controls	= ARRAY_SIZE(mx27vis_aic32x4_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.dapm_widgets	= aic32x4_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.dapm_routes	= aic32x4_dapm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int mx27vis_aic32x4_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct snd_mx27vis_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		dev_err(&pdev->dev, "No platform data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	mx27vis_amp_gain0_gpio = pdata->amp_gain0_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	mx27vis_amp_gain1_gpio = pdata->amp_gain1_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mx27vis_amp_mutel_gpio = pdata->amp_mutel_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	mx27vis_amp_muter_gpio = pdata->amp_muter_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	mx27vis_aic32x4.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ret = devm_snd_soc_register_card(&pdev->dev, &mx27vis_aic32x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Connect SSI0 as clock slave to SSI1 external pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			IMX_AUDMUX_V1_PCR_SYN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			IMX_AUDMUX_V1_PCR_TFSDIR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			IMX_AUDMUX_V1_PCR_TCLKDIR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	imx_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			IMX_AUDMUX_V1_PCR_SYN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct platform_driver mx27vis_aic32x4_audio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.name = "mx27vis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.probe = mx27vis_aic32x4_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) module_platform_driver(mx27vis_aic32x4_audio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DESCRIPTION("ALSA SoC AIC32X4 mx27 visstrim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_ALIAS("platform:mx27vis");