^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef _IMX_SSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define _IMX_SSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define SSI_STX0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define SSI_STX1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define SSI_SRX0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SSI_SRX1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SSI_SCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SSI_SCR_CLK_IST (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SSI_SCR_CLK_IST_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SSI_SCR_TCH_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SSI_SCR_SYS_CLK_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SSI_SCR_I2S_MODE_NORM (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SSI_SCR_I2S_MODE_MSTR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SSI_I2S_MODE_MASK (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SSI_SCR_SYN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SSI_SCR_NET (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SSI_SCR_RE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SSI_SCR_TE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SSI_SCR_SSIEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SSI_SISR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SSI_SISR_MASK ((1 << 19) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SSI_SISR_CMDAU (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSI_SISR_CMDDU (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSI_SISR_RXT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SSI_SISR_RDR1 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSI_SISR_RDR0 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSI_SISR_TDE1 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SSI_SISR_TDE0 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SSI_SISR_ROE1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SSI_SISR_ROE0 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SSI_SISR_TUE1 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SSI_SISR_TUE0 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SSI_SISR_TFS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SSI_SISR_RFS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SSI_SISR_TLS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SSI_SISR_RLS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SSI_SISR_RFF1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SSI_SISR_RFF0 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SSI_SISR_TFE1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SSI_SISR_TFE0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SSI_SIER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SSI_SIER_RDMAE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SSI_SIER_RIE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSI_SIER_TDMAE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SSI_SIER_TIE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SSI_SIER_CMDAU_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SSI_SIER_CMDDU_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SSI_SIER_RXT_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SSI_SIER_RDR1_EN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SSI_SIER_RDR0_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SSI_SIER_TDE1_EN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SSI_SIER_TDE0_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SSI_SIER_ROE1_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SSI_SIER_ROE0_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SSI_SIER_TUE1_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SSI_SIER_TUE0_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SSI_SIER_TFS_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SSI_SIER_RFS_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SSI_SIER_TLS_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SSI_SIER_RLS_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SSI_SIER_RFF1_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SSI_SIER_RFF0_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SSI_SIER_TFE1_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SSI_SIER_TFE0_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SSI_STCR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SSI_STCR_TXBIT0 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SSI_STCR_TFEN1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SSI_STCR_TFEN0 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SSI_FIFO_ENABLE_0_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SSI_STCR_TFDIR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SSI_STCR_TXDIR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SSI_STCR_TSHFD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SSI_STCR_TSCKP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SSI_STCR_TFSI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SSI_STCR_TFSL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SSI_STCR_TEFS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SSI_SRCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SSI_SRCR_RXBIT0 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SSI_SRCR_RFEN1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SSI_SRCR_RFEN0 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SSI_FIFO_ENABLE_0_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SSI_SRCR_RFDIR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SSI_SRCR_RXDIR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SSI_SRCR_RSHFD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SSI_SRCR_RSCKP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SSI_SRCR_RFSI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SSI_SRCR_RFSL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SSI_SRCR_REFS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SSI_SRCCR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SSI_SRCCR_DIV2 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SSI_SRCCR_PSR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SSI_SRCCR_PM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SSI_SRCCR_WL_MASK (0xf << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SSI_SRCCR_DC_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SSI_SRCCR_PM_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SSI_STCCR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SSI_STCCR_DIV2 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SSI_STCCR_PSR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SSI_STCCR_DC(x) (((x) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SSI_STCCR_PM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SSI_STCCR_WL_MASK (0xf << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SSI_STCCR_DC_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SSI_STCCR_PM_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SSI_SFCSR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SSI_RX_FIFO_1_COUNT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SSI_TX_FIFO_1_COUNT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SSI_RX_FIFO_0_COUNT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SSI_TX_FIFO_0_COUNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SSI_SFCSR_RFWM0_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SSI_SFCSR_TFWM0_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SSI_STR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SSI_STR_TEST (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SSI_STR_RCK2TCK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SSI_STR_RFS2TFS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SSI_STR_TXD2RXD (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SSI_STR_TCK2RCK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SSI_STR_TFS2RFS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SSI_SOR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SSI_SOR_CLKOFF (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SSI_SOR_RX_CLR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SSI_SOR_TX_CLR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SSI_SOR_INIT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SSI_SOR_WAIT(x) (((x) & 0x3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SSI_SOR_WAIT_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SSI_SOR_SYNRST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SSI_SACNT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SSI_SACNT_WR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SSI_SACNT_RD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SSI_SACNT_TIF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SSI_SACNT_FV (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SSI_SACNT_AC97EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SSI_SACADD 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SSI_SACDAT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SSI_SATAG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SSI_STMSK 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SSI_SRMSK 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SSI_SACCST 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SSI_SACCEN 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SSI_SACCDIS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* SSI clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX_SSP_SYS_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* SSI audio dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX_SSI_TX_DIV_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX_SSI_TX_DIV_PSR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX_SSI_TX_DIV_PM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX_SSI_RX_DIV_2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX_SSI_RX_DIV_PSR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX_SSI_RX_DIV_PM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DRV_NAME "imx-ssi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct imx_ssi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct platform_device *ac97_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct snd_soc_dai *imx_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int fiq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void (*ac97_reset) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void (*ac97_warm_reset)(struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct snd_dmaengine_dai_dma_data dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct imx_dma_data filter_data_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct imx_dma_data filter_data_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct imx_pcm_fiq_params fiq_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int fiq_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int dma_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif /* _IMX_SSI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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