^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // imx-ssi.c -- ALSA Soc Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // This code is based on code copyrighted by Freescale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Liam Girdwood, Javier Martin and probably others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // The i.MX SSI core has some nasty limitations in AC97 mode. While most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // one FIFO which combines all valid receive slots. We cannot even select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // which slots we want to receive. The WM9712 with which this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // was developed with always sends GPIO status data in slot 12 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) // we receive in our (PCM-) data stream. The only chance we have is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) // manually skip this data in the FIQ handler. With sampling rates different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) // from 48000Hz not every frame has valid receive data, so the ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) // between pcm data and GPIO status data changes. Our FIQ handler is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) // able to handle this, hence this driver only works with 48000Hz sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) // rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) // Reading and writing AC97 registers is another challenge. The core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) // provides us status bits when the read register is updated with *another*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) // value. When we read the same register two times (and the register still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) // contains the same value) these status bits are not set. We work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) // around this by not polling these bits but only wait a fixed delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_data/asoc-imx-ssi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "imx-ssi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "fsl_utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * SSI Network Mode or TDM slots configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Should only be called when port is inactive (i.e. SSIEN = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 sccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sccr = readl(ssi->base + SSI_STCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) sccr &= ~SSI_STCCR_DC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) sccr |= SSI_STCCR_DC(slots - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(sccr, ssi->base + SSI_STCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) sccr = readl(ssi->base + SSI_SRCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) sccr &= ~SSI_STCCR_DC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sccr |= SSI_STCCR_DC(slots - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(sccr, ssi->base + SSI_SRCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(~tx_mask, ssi->base + SSI_STMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(~rx_mask, ssi->base + SSI_SRMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * SSI DAI format configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Should only be called when port is inactive (i.e. SSIEN = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 strcr = 0, scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* DAI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* data on rising edge of bclk, frame low 1clk before data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SSI_STCR_TEFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) scr |= SSI_SCR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) scr &= ~SSI_I2S_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) scr |= SSI_SCR_I2S_MODE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* data on rising edge of bclk, frame high with data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* data on rising edge of bclk, frame high with data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* data on rising edge of bclk, frame high 1clk before data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SSI_STCR_TEFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* DAI clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) strcr ^= SSI_STCR_TSCKP | SSI_STCR_TFSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) strcr ^= SSI_STCR_TSCKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) strcr ^= SSI_STCR_TFSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* DAI clock master masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Master mode not implemented, needs handling of clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) strcr |= SSI_STCR_TFEN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ssi->flags & IMX_SSI_NET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) scr |= SSI_SCR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ssi->flags & IMX_SSI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) scr |= SSI_SCR_SYN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(strcr, ssi->base + SSI_STCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(strcr, ssi->base + SSI_SRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(scr, ssi->base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * SSI system clock configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Should only be called when port is inactive (i.e. SSIEN = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) scr = readl(ssi->base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case IMX_SSP_SYS_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (dir == SND_SOC_CLOCK_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) scr |= SSI_SCR_SYS_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) scr &= ~SSI_SCR_SYS_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(scr, ssi->base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * SSI Clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Should only be called when port is inactive (i.e. SSIEN = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int div_id, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 stccr, srccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) stccr = readl(ssi->base + SSI_STCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) srccr = readl(ssi->base + SSI_SRCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) switch (div_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case IMX_SSI_TX_DIV_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) stccr &= ~SSI_STCCR_DIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) stccr |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case IMX_SSI_TX_DIV_PSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) stccr &= ~SSI_STCCR_PSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) stccr |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case IMX_SSI_TX_DIV_PM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) stccr &= ~0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) stccr |= SSI_STCCR_PM(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case IMX_SSI_RX_DIV_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) stccr &= ~SSI_STCCR_DIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) stccr |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case IMX_SSI_RX_DIV_PSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) stccr &= ~SSI_STCCR_PSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) stccr |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case IMX_SSI_RX_DIV_PM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) stccr &= ~0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) stccr |= SSI_STCCR_PM(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(stccr, ssi->base + SSI_STCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(srccr, ssi->base + SSI_SRCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Should only be called when port is inactive (i.e. SSIEN = 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * although can be called multiple times by upper layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 reg, sccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Tx/Rx config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg = SSI_STCCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg = SSI_SRCCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ssi->flags & IMX_SSI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg = SSI_STCCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* DAI data (word) size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sccr |= SSI_SRCCR_WL(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sccr |= SSI_SRCCR_WL(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sccr |= SSI_SRCCR_WL(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(sccr, ssi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int sier_bits, sier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) scr = readl(ssi->base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sier = readl(ssi->base + SSI_SIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ssi->flags & IMX_SSI_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) sier_bits = SSI_SIER_TDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ssi->flags & IMX_SSI_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sier_bits = SSI_SIER_RDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) scr |= SSI_SCR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) scr |= SSI_SCR_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sier |= sier_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) scr |= SSI_SCR_SSIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) scr &= ~SSI_SCR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) scr &= ~SSI_SCR_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) sier &= ~sier_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!(scr & (SSI_SCR_TE | SSI_SCR_RE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) scr &= ~SSI_SCR_SSIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!(ssi->flags & IMX_SSI_USE_AC97))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* rx/tx are always enabled to access ac97 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(scr, ssi->base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel(sier, ssi->base + SSI_SIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .hw_params = imx_ssi_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .set_fmt = imx_ssi_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .set_clkdiv = imx_ssi_set_dai_clkdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .set_sysclk = imx_ssi_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .trigger = imx_ssi_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) snd_soc_dai_set_drvdata(dai, ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.maxburst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SSI_SFCSR_RFWM0(ssi->dma_params_rx.maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writel(val, ssi->base + SSI_SFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Tx/Rx config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dai->playback_dma_data = &ssi->dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dai->capture_dma_data = &ssi->dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct snd_soc_dai_driver imx_ssi_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .probe = imx_ssi_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .ops = &imx_ssi_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct snd_soc_dai_driver imx_ac97_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .probe = imx_ssi_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .stream_name = "AC97 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .stream_name = "AC97 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .ops = &imx_ssi_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct snd_soc_component_driver imx_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void __iomem *base = imx_ssi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writel(0x0, base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel(0x0, base + SSI_STCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel(0x0, base + SSI_SRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel(SSI_SFCSR_RFWM0(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SSI_SFCSR_TFWM0(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SSI_SFCSR_RFWM1(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel(SSI_SOR_WAIT(3), base + SSI_SOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SSI_SCR_TE | SSI_SCR_RE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) base + SSI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(0xff, base + SSI_SACCDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel(0x300, base + SSI_SACCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct imx_ssi *ac97_ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct imx_ssi *imx_ssi = ac97_ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void __iomem *base = imx_ssi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int lreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (reg > 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) lreg = reg << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel(lreg, base + SSI_SACADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) lval = val << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) writel(lval , base + SSI_SACDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct imx_ssi *imx_ssi = ac97_ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void __iomem *base = imx_ssi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned short val = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int lreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) lreg = (reg & 0x7f) << 12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) writel(lreg, base + SSI_SACADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct imx_ssi *imx_ssi = ac97_ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (imx_ssi->ac97_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) imx_ssi->ac97_reset(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* First read sometimes fails, do a dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) imx_ssi_ac97_read(ac97, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct imx_ssi *imx_ssi = ac97_ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (imx_ssi->ac97_warm_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) imx_ssi->ac97_warm_reset(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* First read sometimes fails, do a dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) imx_ssi_ac97_read(ac97, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct snd_ac97_bus_ops imx_ssi_ac97_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .read = imx_ssi_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .write = imx_ssi_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .reset = imx_ssi_ac97_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .warm_reset = imx_ssi_ac97_warm_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int imx_ssi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct imx_ssi *ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct snd_soc_dai_driver *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_set_drvdata(&pdev->dev, ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ssi->ac97_reset = pdata->ac97_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ssi->ac97_warm_reset = pdata->ac97_warm_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ssi->flags = pdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ssi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ssi->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ssi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ssi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (IS_ERR(ssi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = PTR_ERR(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(&pdev->dev, "Cannot get the clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto failed_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = clk_prepare_enable(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto failed_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ssi->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (IS_ERR(ssi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = PTR_ERR(ssi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto failed_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ssi->flags & IMX_SSI_USE_AC97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ac97_ssi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(&pdev->dev, "AC'97 SSI already registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto failed_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ac97_ssi = ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) setup_channel_to_ac97(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dai = &imx_ac97_dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dai = &imx_ssi_dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(0x0, ssi->base + SSI_SIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ssi->dma_params_rx.addr = res->start + SSI_SRX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ssi->dma_params_tx.addr = res->start + SSI_STX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ssi->dma_params_tx.maxburst = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ssi->dma_params_rx.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ssi->dma_params_tx.filter_data = &ssi->filter_data_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ssi->dma_params_rx.filter_data = &ssi->filter_data_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) imx_pcm_dma_params_init_data(&ssi->filter_data_tx, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) IMX_DMATYPE_SSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) imx_pcm_dma_params_init_data(&ssi->filter_data_rx, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) IMX_DMATYPE_SSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) platform_set_drvdata(pdev, ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = snd_soc_set_ac97_ops(&imx_ssi_ac97_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) goto failed_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = snd_soc_register_component(&pdev->dev, &imx_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(&pdev->dev, "register DAI failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) goto failed_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ssi->fiq_params.irq = ssi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ssi->fiq_params.base = ssi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ssi->dma_init = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ssi->fiq_init && ssi->dma_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = ssi->fiq_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto failed_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) failed_pcm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) failed_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) clk_disable_unprepare(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) failed_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int imx_ssi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct imx_ssi *ssi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!ssi->fiq_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) imx_pcm_fiq_exit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ssi->flags & IMX_SSI_USE_AC97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ac97_ssi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_disable_unprepare(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct platform_driver imx_ssi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .probe = imx_ssi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .remove = imx_ssi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .name = "imx-ssi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) module_platform_driver(imx_ssi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MODULE_ALIAS("platform:imx-ssi");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags