Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // imx-pcm-fiq.c  --  ALSA Soc Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // This code is based on code copyrighted by Freescale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Liam Girdwood, Javier Martin and probably others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/platform_data/asoc-imx-ssi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "imx-ssi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct imx_pcm_runtime_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned int period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct hrtimer hrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int poll_time_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	atomic_t playing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	atomic_t capturing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static enum hrtimer_restart snd_hrtimer_callback(struct hrtimer *hrt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct imx_pcm_runtime_data *iprtd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		container_of(hrt, struct imx_pcm_runtime_data, hrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct snd_pcm_substream *substream = iprtd->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct pt_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	get_fiq_regs(&regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		iprtd->offset = regs.ARM_r8 & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		iprtd->offset = regs.ARM_r9 & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	hrtimer_forward_now(hrt, ns_to_ktime(iprtd->poll_time_ns));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return HRTIMER_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct fiq_handler fh = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int snd_imx_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				 struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				 struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct imx_pcm_runtime_data *iprtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	iprtd->periods = params_periods(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	iprtd->period = params_period_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	iprtd->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	iprtd->poll_time_ns = 1000000000 / params_rate(params) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				params_period_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int snd_imx_pcm_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			       struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct imx_pcm_runtime_data *iprtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct pt_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	get_fiq_regs(&regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	set_fiq_regs(&regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int imx_pcm_fiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int snd_imx_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			       struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct imx_pcm_runtime_data *iprtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			atomic_set(&iprtd->playing, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			atomic_set(&iprtd->capturing, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		      HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		enable_fiq(imx_pcm_fiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			atomic_set(&iprtd->playing, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			atomic_set(&iprtd->capturing, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (!atomic_read(&iprtd->playing) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				!atomic_read(&iprtd->capturing))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			disable_fiq(imx_pcm_fiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) snd_imx_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		    struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct imx_pcm_runtime_data *iprtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return bytes_to_frames(substream->runtime, iprtd->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct snd_pcm_hardware snd_imx_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.period_bytes_min = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.period_bytes_max = 16 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.periods_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.periods_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int snd_imx_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct imx_pcm_runtime_data *iprtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (iprtd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	runtime->private_data = iprtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	iprtd->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	atomic_set(&iprtd->playing, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	atomic_set(&iprtd->capturing, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	hrtimer_init(&iprtd->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	iprtd->hrt.function = snd_hrtimer_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ret = snd_pcm_hw_constraint_integer(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		kfree(iprtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int snd_imx_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			 struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct imx_pcm_runtime_data *iprtd = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	hrtimer_cancel(&iprtd->hrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	kfree(iprtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int snd_imx_pcm_mmap(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			    struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			    struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = dma_mmap_wc(substream->pcm->card->dev, vma, runtime->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			  runtime->dma_addr, runtime->dma_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	pr_debug("%s: ret: %d %p %pad 0x%08zx\n", __func__, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			runtime->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			&runtime->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			runtime->dma_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct snd_dma_buffer *buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	size_t size = IMX_SSI_DMABUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	buf->dev.type = SNDRV_DMA_TYPE_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	buf->dev.dev = pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	buf->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	buf->area = dma_alloc_wc(pcm->card->dev, size, &buf->addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!buf->area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	buf->bytes = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ret = imx_pcm_preallocate_dma_buffer(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		ret = imx_pcm_preallocate_dma_buffer(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			SNDRV_PCM_STREAM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int ssi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int snd_imx_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			   struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ret = imx_pcm_new(rtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		struct snd_dma_buffer *buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		imx_ssi_fiq_tx_buffer = (unsigned long)buf->area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		struct snd_dma_buffer *buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		imx_ssi_fiq_rx_buffer = (unsigned long)buf->area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	set_fiq_handler(&imx_ssi_fiq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		&imx_ssi_fiq_end - &imx_ssi_fiq_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void imx_pcm_free(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct snd_dma_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	for (stream = 0; stream < 2; stream++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		substream = pcm->streams[stream].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		if (!substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		buf = &substream->dma_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		if (!buf->area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dma_free_wc(pcm->card->dev, buf->bytes, buf->area, buf->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		buf->area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void snd_imx_pcm_free(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			     struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mxc_set_irq_fiq(ssi_irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	release_fiq(&fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	imx_pcm_free(pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct snd_soc_component_driver imx_soc_component_fiq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.open		= snd_imx_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.close		= snd_imx_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.hw_params	= snd_imx_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.prepare	= snd_imx_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.trigger	= snd_imx_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.pointer	= snd_imx_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.mmap		= snd_imx_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.pcm_construct	= snd_imx_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.pcm_destruct	= snd_imx_pcm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int imx_pcm_fiq_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		struct imx_pcm_fiq_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	ret = claim_fiq(&fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		dev_err(&pdev->dev, "failed to claim fiq: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	mxc_set_irq_fiq(params->irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ssi_irq = params->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	imx_pcm_fiq = params->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	imx_ssi_fiq_base = (unsigned long)params->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	params->dma_params_tx->maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	params->dma_params_rx->maxburst = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ret = devm_snd_soc_register_component(&pdev->dev, &imx_soc_component_fiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 					      NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		goto failed_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) failed_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	mxc_set_irq_fiq(ssi_irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	release_fiq(&fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) EXPORT_SYMBOL_GPL(imx_pcm_fiq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void imx_pcm_fiq_exit(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) EXPORT_SYMBOL_GPL(imx_pcm_fiq_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_LICENSE("GPL");