^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Timur Tabi <timur@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2007-2008 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MPC8610_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MPC8610_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* -- SSI Register Map -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* SSI Transmit Data Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_SSI_STX0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* SSI Transmit Data Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_SSI_STX1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* SSI Receive Data Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_SSI_SRX0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* SSI Receive Data Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_SSI_SRX1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* SSI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_SSI_SCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* SSI Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_SSI_SISR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* SSI Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_SSI_SIER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SSI Transmit Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_SSI_STCR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SSI Receive Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_SSI_SRCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* SSI Transmit Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_SSI_STCCR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* SSI Receive Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_SSI_SRCCR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* SSI FIFO Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_SSI_SFCSR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * SSI Test Register (Intended for debugging purposes only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Note: STR is not documented in recent IMX datasheet, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * is described in IMX51 reference manual at section 56.3.3.14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_SSI_STR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * SSI Option Register (Intended for internal use only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Note: SOR is not documented in recent IMX datasheet, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * is described in IMX51 reference manual at section 56.3.3.15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_SSI_SOR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* SSI AC97 Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_SSI_SACNT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* SSI AC97 Command Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_SSI_SACADD 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* SSI AC97 Command Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_SSI_SACDAT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* SSI AC97 Tag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_SSI_SATAG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* SSI Transmit Time Slot Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_SSI_STMSK 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* SSI Receive Time Slot Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_SSI_SRMSK 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * SSI AC97 Channel Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * The status could be changed by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_SSI_SACCST 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* SSI AC97 Channel Enable Register -- Set bits in SACCST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_SSI_SACCEN 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_SSI_SACCDIS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* -- SSI Register Field Maps -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* SSI Control Register -- REG_SSI_SCR 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SSI_SCR_SYNC_TX_FS 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SSI_SCR_RFR_CLK_DIS 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SSI_SCR_TFR_CLK_DIS 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SSI_SCR_TCH_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SSI_SCR_SYS_CLK_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SSI_SCR_I2S_MODE_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SSI_SCR_I2S_MODE_NORMAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SSI_SCR_I2S_MODE_MASTER 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SSI_SCR_I2S_MODE_SLAVE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SSI_SCR_SYN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SSI_SCR_NET 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SSI_SCR_I2S_NET_MASK (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SSI_SCR_RE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SSI_SCR_TE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SSI_SCR_SSIEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SSI_SISR_RFRC 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SSI_SISR_TFRC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SSI_SISR_CMDAU 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SSI_SISR_CMDDU 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SSI_SISR_RXT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SSI_SISR_RDR1 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SSI_SISR_RDR0 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SSI_SISR_TDE1 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SSI_SISR_TDE0 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SSI_SISR_ROE1 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SSI_SISR_ROE0 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SSI_SISR_TUE1 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SSI_SISR_TUE0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SSI_SISR_TFS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SSI_SISR_RFS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SSI_SISR_TLS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SSI_SISR_RLS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SSI_SISR_RFF1 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SSI_SISR_RFF0 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SSI_SISR_TFE1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SSI_SISR_TFE0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SSI_SIER_RFRC_EN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SSI_SIER_TFRC_EN 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SSI_SIER_RDMAE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SSI_SIER_RIE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SSI_SIER_TDMAE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SSI_SIER_TIE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SSI_SIER_CMDAU_EN 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SSI_SIER_CMDDU_EN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SSI_SIER_RXT_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SSI_SIER_RDR1_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SSI_SIER_RDR0_EN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SSI_SIER_TDE1_EN 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SSI_SIER_TDE0_EN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SSI_SIER_ROE1_EN 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SSI_SIER_ROE0_EN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SSI_SIER_TUE1_EN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SSI_SIER_TUE0_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SSI_SIER_TFS_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SSI_SIER_RFS_EN 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SSI_SIER_TLS_EN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SSI_SIER_RLS_EN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SSI_SIER_RFF1_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SSI_SIER_RFF0_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SSI_SIER_TFE1_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SSI_SIER_TFE0_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SSI_STCR_TXBIT0 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SSI_STCR_TFEN1 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SSI_STCR_TFEN0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SSI_STCR_TFDIR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SSI_STCR_TXDIR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SSI_STCR_TSHFD 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SSI_STCR_TSCKP 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SSI_STCR_TFSI 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SSI_STCR_TFSL 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SSI_STCR_TEFS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SSI_SRCR_RXEXT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SSI_SRCR_RXBIT0 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SSI_SRCR_RFEN1 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SSI_SRCR_RFEN0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SSI_SRCR_RFDIR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SSI_SRCR_RXDIR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SSI_SRCR_RSHFD 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SSI_SRCR_RSCKP 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SSI_SRCR_RFSI 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SSI_SRCR_RFSL 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SSI_SRCR_REFS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SSI_SxCCR_DIV2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SSI_SxCCR_DIV2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SSI_SxCCR_PSR_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SSI_SxCCR_PSR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SSI_SxCCR_WL_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SSI_SxCCR_WL_MASK 0x0001E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SSI_SxCCR_WL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SSI_SxCCR_DC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SSI_SxCCR_DC_MASK 0x00001F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SSI_SxCCR_DC(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SSI_SxCCR_PM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SSI_SxCCR_PM_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SSI_SxCCR_PM(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SSI_SFCSR_RFCNT1_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SSI_SFCSR_RFCNT1_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SSI_SFCSR_RFCNT1(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SSI_SFCSR_TFCNT1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SSI_SFCSR_TFCNT1_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SSI_SFCSR_TFCNT1(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SSI_SFCSR_RFWM1_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SSI_SFCSR_RFWM1_MASK 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SSI_SFCSR_RFWM1(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SSI_SFCSR_TFWM1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SSI_SFCSR_TFWM1_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SSI_SFCSR_TFWM1(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SSI_SFCSR_RFCNT0_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SSI_SFCSR_RFCNT0_MASK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SSI_SFCSR_RFCNT0(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SSI_SFCSR_TFCNT0_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SSI_SFCSR_TFCNT0_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SSI_SFCSR_TFCNT0(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SSI_SFCSR_RFWM0_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SSI_SFCSR_RFWM0_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SSI_SFCSR_RFWM0(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SSI_SFCSR_TFWM0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SSI_SFCSR_TFWM0_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SSI_SFCSR_TFWM0(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* SSI Test Register -- REG_SSI_STR 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SSI_STR_TEST 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SSI_STR_RCK2TCK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SSI_STR_RFS2TFS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SSI_STR_TXD2RXD 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SSI_STR_TCK2RCK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SSI_STR_TFS2RFS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SSI_STR_TXSTATE(x) ((x) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* SSI Option Register -- REG_SSI_SOR 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SSI_SOR_CLKOFF 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SSI_SOR_RX_CLR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SSI_SOR_TX_CLR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SSI_SOR_INIT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SSI_SOR_WAIT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SSI_SOR_WAIT_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SSI_SOR_SYNRST 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SSI_SACNT_WR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SSI_SACNT_RD 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SSI_SACNT_RDWR_MASK 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SSI_SACNT_TIF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SSI_SACNT_FV 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SSI_SACNT_AC97EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #if IS_ENABLED(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct fsl_ssi_dbg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct dentry *dbg_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int rfrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int tfrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int cmdau;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int cmddu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int rxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int rdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int rdr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int tde1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int tde0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int roe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int roe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int tue1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int tue0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int tfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int rfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int tls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int rls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int rff1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int rff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int tfe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int tfe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct fsl_ssi_dbg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags