^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Timur Tabi <timur@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2007-2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // The i.MX SSI core has some nasty limitations in AC97 mode. While most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // one FIFO which combines all valid receive slots. We cannot even select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // which slots we want to receive. The WM9712 with which this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) // was developed with always sends GPIO status data in slot 12 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) // we receive in our (PCM-) data stream. The only chance we have is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) // manually skip this data in the FIQ handler. With sampling rates different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) // from 48000Hz not every frame has valid receive data, so the ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) // between pcm data and GPIO status data changes. Our FIQ handler is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) // able to handle this, hence this driver only works with 48000Hz sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) // rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) // Reading and writing AC97 registers is another challenge. The core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) // provides us status bits when the read register is updated with *another*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) // value. When we read the same register two times (and the register still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) // contains the same value) these status bits are not set. We work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) // around this by not polling these bits but only wait a fixed delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "fsl_ssi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * The SSI has a limitation in that the samples must be in the same byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * order as the host CPU. This is because when multiple bytes are written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * to the STX register, the bytes and bits must be written in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * order. The STX is a shift register, so all the bits need to be aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * (bit-endianness must match byte-endianness). Processors typically write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * the bits within a byte in the same order that the bytes of a word are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * written in. So if the host CPU is big-endian, then only big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * samples will be written to STX properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FSLSSI_I2S_FORMATS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SNDRV_PCM_FMTBIT_S16_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SNDRV_PCM_FMTBIT_S18_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SNDRV_PCM_FMTBIT_S20_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SNDRV_PCM_FMTBIT_S24_3BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SNDRV_PCM_FMTBIT_S24_BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FSLSSI_I2S_FORMATS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SNDRV_PCM_FMTBIT_S18_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * - Also have NB_NF to mark these two clocks will not be inverted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FSLSSI_AC97_DAIFMT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (SND_SOC_DAIFMT_AC97 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SND_SOC_DAIFMT_CBM_CFS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SND_SOC_DAIFMT_NB_NF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FSLSSI_SIER_DBG_RX_FLAGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (SSI_SIER_RFF0_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SSI_SIER_RLS_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SSI_SIER_RFS_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SSI_SIER_ROE0_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SSI_SIER_RFRC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FSLSSI_SIER_DBG_TX_FLAGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (SSI_SIER_TFE0_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SSI_SIER_TLS_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SSI_SIER_TFS_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SSI_SIER_TUE0_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SSI_SIER_TFRC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum fsl_ssi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FSL_SSI_MCP8610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FSL_SSI_MX21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FSL_SSI_MX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FSL_SSI_MX51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct fsl_ssi_regvals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 sier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 srcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 stcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case REG_SSI_SACCEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case REG_SSI_SACCDIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case REG_SSI_STX0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case REG_SSI_STX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case REG_SSI_SRX0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case REG_SSI_SRX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case REG_SSI_SISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case REG_SSI_SFCSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case REG_SSI_SACNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case REG_SSI_SACADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case REG_SSI_SACDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case REG_SSI_SATAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case REG_SSI_SACCST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case REG_SSI_SOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case REG_SSI_SRX0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case REG_SSI_SRX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case REG_SSI_SISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case REG_SSI_SACADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case REG_SSI_SACDAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case REG_SSI_SATAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case REG_SSI_SRX0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case REG_SSI_SRX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case REG_SSI_SACCST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct regmap_config fsl_ssi_regconfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .max_register = REG_SSI_SACCDIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .val_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .readable_reg = fsl_ssi_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .volatile_reg = fsl_ssi_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .precious_reg = fsl_ssi_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .writeable_reg = fsl_ssi_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct fsl_ssi_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool offline_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 sisr_write_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * struct fsl_ssi - per-SSI private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @regs: Pointer to the regmap registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @irq: IRQ of this SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @cpu_dai_drv: CPU DAI driver for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @dai_fmt: DAI configuration this device is currently used with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @i2s_net: I2S and Network mode configurations of SCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * (this is the initial settings based on the DAI format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @use_dma: DMA is used or FIQ with stream filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @use_dual_fifo: DMA with support for dual FIFO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @fifo_depth: Depth of the SSI FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @slot_width: Width of each DAI slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @slots: Number of slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @regvals: Specific RX/TX register settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @clk: Clock source to access register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @baudclk: Clock source to generate bit and frame-sync clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @baudclk_streams: Active streams that are using baudclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @regcache_sfcsr: Cache sfcsr register value during suspend and resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @regcache_sacnt: Cache sacnt register value during suspend and resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @dma_params_tx: DMA transmit parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @dma_params_rx: DMA receive parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @ssi_phys: physical address of the SSI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @fiq_params: FIQ stream filtering parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @card_pdev: Platform_device pointer to register a sound card for PowerPC or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * to register a CODEC platform device for AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @card_name: Platform_device name to register a sound card for PowerPC or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * to register a CODEC platform device for AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @card_idx: The index of SSI to register a sound card for PowerPC or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * to register a CODEC platform device for AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @dbg_stats: Debugging statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @soc: SoC specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @dev: Pointer to &pdev->dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @fifo_watermark or fewer words in TX fifo or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @fifo_watermark or more empty words in RX fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @dma_maxburst: Max number of words to transfer in one go. So far,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * this is always the same as fifo_watermark.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct fsl_ssi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct regmap *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct snd_soc_dai_driver cpu_dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int dai_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 i2s_net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool synchronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bool use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool use_dual_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bool has_ipg_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct fsl_ssi_regvals regvals[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct clk *baudclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int baudclk_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 regcache_sfcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 regcache_sacnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct snd_dmaengine_dai_dma_data dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dma_addr_t ssi_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct imx_pcm_fiq_params fiq_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct platform_device *card_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) char card_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 card_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct fsl_ssi_dbg dbg_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct fsl_ssi_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 fifo_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 dma_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct mutex ac97_reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * SoC specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * 1) SSI in earlier SoCS has critical bits in control registers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * cannot be changed after SSI starts running -- a software reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * (set SSIEN to 0) is required to change their values. So adding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * an offline_config flag for these SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * 2) SDMA is available since imx35. However, imx35 does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * DMA bits changing when SSI is running, so set offline_config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 3) imx51 and later versions support register configurations when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * SSI is running (SSIEN); For these versions, DMA needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * configured before SSI sends DMA request to avoid an undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * DMA request on the SDMA side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .imx = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .offline_config = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SSI_SISR_ROE0 | SSI_SISR_ROE1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SSI_SISR_TUE0 | SSI_SISR_TUE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .imx = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .imx21regs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .offline_config = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .sisr_write_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .imx = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .offline_config = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SSI_SISR_ROE0 | SSI_SISR_ROE1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SSI_SISR_TUE0 | SSI_SISR_TUE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .imx = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .offline_config = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SSI_SISR_TUE0 | SSI_SISR_TUE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct of_device_id fsl_ssi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SND_SOC_DAIFMT_AC97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SND_SOC_DAIFMT_CBS_CFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SND_SOC_DAIFMT_CBM_CFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * fsl_ssi_irq - Interrupt handler to gather states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @irq: irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @dev_id: context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct fsl_ssi *ssi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 sisr, sisr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_read(regs, REG_SSI_SISR, &sisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sisr2 = sisr & ssi->soc->sisr_write_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Clear the bits that we set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (sisr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) regmap_write(regs, REG_SSI_SISR, sisr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * cached values in regvals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @ssi: SSI context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * @tx: direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * 1) For offline_config SoCs, enable all necessary bits of both streams
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * when 1st stream starts, even if the opposite stream will not start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * 2) It also clears FIFO before setting regvals; SOR is safe to set online
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct fsl_ssi_regvals *vals = ssi->regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int dir = tx ? TX : RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 sier, srcr, stcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Clear dirty data in the FIFO; It also prevents channel slipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) regmap_update_bits(ssi->regs, REG_SSI_SOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * On offline_config SoCs, SxCR and SIER are already configured when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * the previous stream started. So skip all SxCR and SIER settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * to prevent online reconfigurations, then jump to set SCR directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ssi->soc->offline_config && ssi->streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) goto enable_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ssi->soc->offline_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Online reconfiguration not supported, so enable all bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * both streams at once to avoid necessity of reconfigurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) srcr = vals[RX].srcr | vals[TX].srcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) stcr = vals[RX].stcr | vals[TX].stcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sier = vals[RX].sier | vals[TX].sier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Otherwise, only set bits for the current stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) srcr = vals[dir].srcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) stcr = vals[dir].stcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sier = vals[dir].sier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Configure SRCR, STCR and SIER at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) enable_scr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Start DMA before setting TE to avoid FIFO underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * which may cause a channel slip or a channel swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * TODO: FIQ cases might also need this upon testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ssi->use_dma && tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int try = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 sfcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Enable SSI first to send TX DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regmap_update_bits(ssi->regs, REG_SSI_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SSI_SCR_SSIEN, SSI_SCR_SSIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Busy wait until TX FIFO not empty -- DMA working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (SSI_SFCSR_TFCNT0(sfcsr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } while (--try);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* FIFO still empty -- something might be wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!SSI_SFCSR_TFCNT0(sfcsr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Enable all remaining bits in SCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) regmap_update_bits(ssi->regs, REG_SSI_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) vals[dir].scr, vals[dir].scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Log the enabled stream to the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ssi->streams |= BIT(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Exclude bits that are used by the opposite stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * When both streams are active, disabling some bits for the current stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * might break the other stream if these bits are used by it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @vals : regvals of the current stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @avals: regvals of the opposite stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * @aactive: active state of the opposite stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * 1) XOR vals and avals to get the differences if the other stream is active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Otherwise, return current vals if the other stream is not active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * 2) AND the result of 1) with the current vals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define _ssi_xor_shared_bits(vals, avals, aactive) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ((vals) ^ ((avals) * (aactive)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define ssi_excl_shared_bits(vals, avals, aactive) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * with cached values in regvals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * @ssi: SSI context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @tx: direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * 1) For offline_config SoCs, to avoid online reconfigurations, disable all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * bits of both streams at once when the last stream is abort to end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct fsl_ssi_regvals *vals, *avals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 sier, srcr, stcr, scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int adir = tx ? RX : TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int dir = tx ? TX : RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bool aactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Check if the opposite stream is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) aactive = ssi->streams & BIT(adir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) vals = &ssi->regvals[dir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Get regvals of the opposite stream to keep opposite stream safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) avals = &ssi->regvals[adir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * To keep the other stream safe, exclude shared bits between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * both streams, and get safe bits to disable current stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Disable safe bits of SCR register for the current stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Log the disabled stream to the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ssi->streams &= ~BIT(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * On offline_config SoCs, if the other stream is active, skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * SxCR and SIER settings to prevent online reconfigurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ssi->soc->offline_config && aactive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto fifo_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ssi->soc->offline_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Now there is only current stream active, disable all bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) srcr = vals->srcr | avals->srcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) stcr = vals->stcr | avals->stcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sier = vals->sier | avals->sier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * To keep the other stream safe, exclude shared bits between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * both streams, and get safe bits to disable current stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Clear configurations of SRCR, STCR and SIER at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) fifo_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Clear remaining data in the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) regmap_update_bits(ssi->regs, REG_SSI_SOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!ssi->soc->imx21regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Disable all channel slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) regmap_write(regs, REG_SSI_SACCDIS, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) regmap_write(regs, REG_SSI_SACCEN, 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * SCR to later set them safely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * @ssi: SSI context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct fsl_ssi_regvals *vals = ssi->regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) vals[RX].srcr = SSI_SRCR_RFEN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) vals[TX].stcr = SSI_STCR_TFEN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* AC97 has already enabled SSIEN, RE and TE, so ignore them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (fsl_ssi_is_ac97(ssi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) vals[RX].scr = vals[TX].scr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ssi->use_dual_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) vals[RX].srcr |= SSI_SRCR_RFEN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) vals[TX].stcr |= SSI_STCR_TFEN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ssi->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) vals[RX].sier |= SSI_SIER_RDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) vals[TX].sier |= SSI_SIER_TDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vals[RX].sier |= SSI_SIER_RIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) vals[TX].sier |= SSI_SIER_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Setup the clock control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Enable AC97 mode and startup the SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* AC97 has to communicate with codec before starting a stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) regmap_update_bits(regs, REG_SSI_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int fsl_ssi_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = clk_prepare_enable(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * When using dual fifo mode, it is safer to ensure an even period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * size. If appearing to an odd number while DMA always starts its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * task from fifo0, fifo1 would be neglected at the end of each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * period. But SSI would still access fifo1 with an invalid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ssi->use_dual_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) snd_pcm_hw_constraint_step(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) clk_disable_unprepare(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @substream: ASoC substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * @dai: pointer to DAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @hw_params: pointers to hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Notes: This function can be only called when using SSI as DAI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * Quick instruction for parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * freq: Output BCLK frequency = samplerate * slots * slot_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * (In 2-channel I2S Master mode, slot_width is fixed 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned long clkrate, baudrate, tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int channels = params_channels(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int slot_width = params_width(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) unsigned int slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u64 sub, savesub = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) bool baudclk_is_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Override slots and slot_width if being specifically set... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ssi->slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) slots = ssi->slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ssi->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) slot_width = ssi->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* ...but force 32 bits for stereo audio using I2S Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (channels == 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) slot_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Generate bit clock based on the slot number and slot width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) freq = slots * slot_width * params_rate(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Don't apply it to any non-baudclk circumstance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (IS_ERR(ssi->baudclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Hardware limitation: The bclk rate must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * never greater than 1/5 IPG clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (freq * 5 > clk_get_rate(ssi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(dai->dev, "bitclk > ipgclk / 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* It should be already enough to divide clock by setting pm alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) psr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) div2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) factor = (div2 + 1) * (7 * psr + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) for (i = 0; i < 255; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tmprate = freq * factor * (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (baudclk_is_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) clkrate = clk_get_rate(ssi->baudclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clkrate = clk_round_rate(ssi->baudclk, tmprate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clkrate /= factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) afreq = clkrate / (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (freq == afreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) sub = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else if (freq / afreq == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) sub = freq - afreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) else if (afreq / freq == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sub = afreq - freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Calculate the fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) sub *= 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) do_div(sub, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) baudrate = tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) savesub = sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pm = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* We are lucky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (savesub == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* No proper pm found if it is still remaining the initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (pm == 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(dai->dev, "failed to handle the required sysclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (psr ? SSI_SxCCR_PSR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* STCCR is used for RX in synchronous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tx2 = tx || ssi->synchronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!baudclk_is_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = clk_set_rate(ssi->baudclk, baudrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(dai->dev, "failed to set baudclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @substream: ASoC substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * @hw_params: pointers to hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * @dai: pointer to DAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * disabled on offline_config SoCs. Even for online configurable SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * running in synchronous mode (both TX and RX use STCCR), it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * safe to re-configure them when both two streams start running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * fsl_ssi_set_bclk() if SSI is the DAI clock master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct snd_pcm_hw_params *hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned int channels = params_channels(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned int sample_size = params_width(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 wl = SSI_SxCCR_WL(sample_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (fsl_ssi_is_i2s_master(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = fsl_ssi_set_bclk(substream, dai, hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Do not enable the clock if it is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!(ssi->baudclk_streams & BIT(substream->stream))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = clk_prepare_enable(ssi->baudclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ssi->baudclk_streams |= BIT(substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * SSI is properly configured if it is enabled and running in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * the synchronous mode; Note that AC97 mode is an exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * that should set separate configurations for STCCR and SRCCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * despite running in the synchronous mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ssi->streams && ssi->synchronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * Keep the ssi->i2s_net intact while having a local variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * to override settings for special use cases. Otherwise, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * ssi->i2s_net will lose the settings for regular use cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 i2s_net = ssi->i2s_net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Normal + Network mode to send 16-bit data in 32-bit frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Use Normal mode to send mono data at 1st slot of 2 slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) i2s_net = SSI_SCR_I2S_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) regmap_update_bits(regs, REG_SSI_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SSI_SCR_I2S_NET_MASK, i2s_net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* In synchronous mode, the SSI uses STCCR for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) tx2 = tx || ssi->synchronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (fsl_ssi_is_i2s_master(ssi) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ssi->baudclk_streams & BIT(substream->stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) clk_disable_unprepare(ssi->baudclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ssi->baudclk_streams &= ~BIT(substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 strcr = 0, scr = 0, stcr, srcr, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ssi->dai_fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Synchronize frame sync clock for TE to avoid data slipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) scr |= SSI_SCR_SYNC_TX_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Set to default shifting settings: LSB_ALIGNED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) strcr |= SSI_STCR_TXBIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Use Network mode as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ssi->i2s_net = SSI_SCR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (IS_ERR(ssi->baudclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_err(ssi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "missing baudclk for master mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) slots = ssi->slots ? : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) regmap_update_bits(ssi->regs, REG_SSI_STCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Data on rising edge of bclk, frame low, 1clk before data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Data on rising edge of bclk, frame high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) strcr |= SSI_STCR_TSCKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Data on rising edge of bclk, frame high, 1clk before data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Data on rising edge of bclk, frame high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case SND_SOC_DAIFMT_AC97:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* Data on falling edge of bclk, frame high, 1clk before data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) strcr |= SSI_STCR_TEFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) scr |= ssi->i2s_net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* DAI clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Nothing to do for both normal cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Invert bit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) strcr ^= SSI_STCR_TSCKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Invert frame clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) strcr ^= SSI_STCR_TFSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Invert both clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) strcr ^= SSI_STCR_TSCKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) strcr ^= SSI_STCR_TFSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* DAI clock master masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Output bit and frame sync clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) scr |= SSI_SCR_SYS_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Input bit or frame sync clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Input bit clock but output frame sync clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) strcr |= SSI_STCR_TFDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) stcr = strcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) srcr = strcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) srcr &= ~SSI_SRCR_RXDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) scr |= SSI_SCR_SYN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * @dai: pointer to DAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * @fmt: format mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* AC97 configured DAIFMT earlier in the probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (fsl_ssi_is_ac97(ssi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return _fsl_ssi_set_dai_fmt(ssi, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * @dai: pointer to DAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * @tx_mask: mask for TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * @rx_mask: mask for RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * @slots: number of slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * @slot_width: number of bits per slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) u32 rx_mask, int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* The slot number should be >= 2 if using Network mode or I2S mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (ssi->i2s_net && slots < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) regmap_update_bits(regs, REG_SSI_STCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) regmap_update_bits(regs, REG_SSI_SRCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* Save the SCR register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) regmap_read(regs, REG_SSI_SCR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Temporarily enable SSI to allow SxMSKs to be configurable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Restore the value of SSIEN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ssi->slot_width = slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ssi->slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * @substream: ASoC substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * @cmd: trigger command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * @dai: pointer to DAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * The DMA channel is in external master start and pause mode, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * means the SSI completely controls the flow of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * SACCST might be modified via AC Link by a CODEC if it sends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * extra bits in their SLOTREQ requests, which'll accidentally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * send valid data to slots other than normal playback slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * To be safe, configure SACCST right before TX starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (tx && fsl_ssi_is_ac97(ssi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) fsl_ssi_tx_ac97_saccst_setup(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) fsl_ssi_config_enable(ssi, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) fsl_ssi_config_disable(ssi, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (ssi->soc->imx && ssi->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) &ssi->dma_params_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .startup = fsl_ssi_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .shutdown = fsl_ssi_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .hw_params = fsl_ssi_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .hw_free = fsl_ssi_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .set_fmt = fsl_ssi_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .trigger = fsl_ssi_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static struct snd_soc_dai_driver fsl_ssi_dai_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .probe = fsl_ssi_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .stream_name = "CPU-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .rates = SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .formats = FSLSSI_I2S_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .stream_name = "CPU-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .rates = SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .formats = FSLSSI_I2S_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .ops = &fsl_ssi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const struct snd_soc_component_driver fsl_ssi_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .name = "fsl-ssi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .symmetric_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .probe = fsl_ssi_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .stream_name = "AC97 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .stream_name = "AC97 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* 16-bit capture is broken (errata ERR003778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .formats = SNDRV_PCM_FMTBIT_S20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .ops = &fsl_ssi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static struct fsl_ssi *fsl_ac97_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct regmap *regs = fsl_ac97_data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unsigned int lreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned int lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (reg > 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mutex_lock(&fsl_ac97_data->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret = clk_prepare_enable(fsl_ac97_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pr_err("ac97 write clk_prepare_enable failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) goto ret_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) lreg = reg << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) regmap_write(regs, REG_SSI_SACADD, lreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) lval = val << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) regmap_write(regs, REG_SSI_SACDAT, lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) regmap_update_bits(regs, REG_SSI_SACNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) clk_disable_unprepare(fsl_ac97_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ret_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct regmap *regs = fsl_ac97_data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) unsigned short val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) unsigned int lreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) mutex_lock(&fsl_ac97_data->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = clk_prepare_enable(fsl_ac97_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) goto ret_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) lreg = (reg & 0x7f) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) regmap_write(regs, REG_SSI_SACADD, lreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) regmap_update_bits(regs, REG_SSI_SACNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) regmap_read(regs, REG_SSI_SACDAT, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) val = (reg_val >> 4) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) clk_disable_unprepare(fsl_ac97_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .read = fsl_ssi_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .write = fsl_ssi_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * fsl_ssi_hw_init - Initialize SSI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * @ssi: SSI context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u32 wm = ssi->fifo_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Initialize regvals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) fsl_ssi_setup_regvals(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Set watermarks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) regmap_write(ssi->regs, REG_SSI_SFCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* Enable Dual FIFO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (ssi->use_dual_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) regmap_update_bits(ssi->regs, REG_SSI_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* AC97 should start earlier to communicate with CODECs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) fsl_ssi_setup_ac97(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * fsl_ssi_hw_clean - Clear SSI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * @ssi: SSI context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Disable registers for AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* Disable TE and RE bits first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) regmap_update_bits(ssi->regs, REG_SSI_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) SSI_SCR_TE | SSI_SCR_RE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* Disable AC97 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) regmap_write(ssi->regs, REG_SSI_SACNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* Unset WAIT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) regmap_write(ssi->regs, REG_SSI_SOR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Disable SSI -- software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Make every character in a string lower-case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static void make_lowercase(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) for (; *s; s++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) *s = tolower(*s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int fsl_ssi_imx_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct fsl_ssi *ssi, void __iomem *iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Backward compatible for a DT without ipg clock name assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (ssi->has_ipg_clk_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ssi->clk = devm_clk_get(dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ssi->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (IS_ERR(ssi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = PTR_ERR(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(dev, "failed to get clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* Enable the clock since regmap will not handle it in this case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (!ssi->has_ipg_clk_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = clk_prepare_enable(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* Do not error out for slave cases that live without a baud clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ssi->baudclk = devm_clk_get(dev, "baud");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (IS_ERR(ssi->baudclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dev_dbg(dev, "failed to get baud clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PTR_ERR(ssi->baudclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Use even numbers to avoid channel swap due to SDMA script design */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (ssi->use_dual_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ssi->dma_params_tx.maxburst &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ssi->dma_params_rx.maxburst &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!ssi->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * Some boards use an incompatible codec. Use imx-fiq-pcm-audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * to get it working, as DMA is not possible in this situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ssi->fiq_params.irq = ssi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ssi->fiq_params.base = iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) goto error_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) goto error_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) error_pcm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!ssi->has_ipg_clk_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) clk_disable_unprepare(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (!ssi->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) imx_pcm_fiq_exit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (!ssi->has_ipg_clk_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) clk_disable_unprepare(ssi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct device *dev = ssi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) const char *p, *sprop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) const __be32 *iprop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u32 dmas[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) of_id = of_match_device(fsl_ssi_ids, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!of_id || !of_id->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ssi->soc = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret = of_property_match_string(np, "clock-names", "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Get error code if not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ssi->has_ipg_clk_name = ret >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Check if being used in AC97 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) sprop = of_get_property(np, "fsl,mode", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (sprop && !strcmp(sprop, "ac97-slave")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_err(dev, "failed to get SSI index property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) strcpy(ssi->card_name, "ac97-codec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * In synchronous mode, STCK and STFS ports are used by RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * as well. So the software should limit the sample rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * sample bits and channels to be symmetric.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * in the SSI synchronous mode however it does not have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * limit symmetric sample rates and sample bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ssi->synchronous = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* Select DMA or FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* Fetch FIFO depth; Set to 8 for older DT without this property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) iprop = of_get_property(np, "fsl,fifo-depth", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (iprop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ssi->fifo_depth = be32_to_cpup(iprop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ssi->fifo_depth = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* Use dual FIFO mode depending on the support from SDMA script */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = of_property_read_u32_array(np, "dmas", dmas, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ssi->use_dual_fifo = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * Backward compatible for older bindings by manually triggering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * machine driver's probe(). Use /compatible property, including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * address of CPU DAI driver structure, as the name of machine driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * If card_name is set by AC97 earlier, bypass here since it uses a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * different name to register the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct device_node *root = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) sprop = of_get_property(root, "compatible", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) of_node_put(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* Strip "fsl," in the compatible name if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) p = strrchr(sprop, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) sprop = p + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) snprintf(ssi->card_name, sizeof(ssi->card_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) "snd-soc-%s", sprop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) make_lowercase(ssi->card_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ssi->card_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static int fsl_ssi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct regmap_config regconfig = fsl_ssi_regconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct fsl_ssi *ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (!ssi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ssi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Probe from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ret = fsl_ssi_probe_from_dt(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) sizeof(fsl_ssi_ac97_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) fsl_ac97_data = ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) sizeof(fsl_ssi_dai_template));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ssi->cpu_dai_drv.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) iomem = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (IS_ERR(iomem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return PTR_ERR(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ssi->ssi_phys = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (ssi->soc->imx21regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* No SACC{ST,EN,DIS} regs in imx21-class SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) regconfig.max_register = REG_SSI_SRMSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) regconfig.num_reg_defaults_raw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) REG_SSI_SRMSK / sizeof(uint32_t) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ssi->has_ipg_clk_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ®config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (IS_ERR(ssi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) dev_err(dev, "failed to init register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return PTR_ERR(ssi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) ssi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (ssi->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return ssi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* Set software limitations for synchronous mode except AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ssi->cpu_dai_drv.symmetric_rates = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ssi->cpu_dai_drv.symmetric_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ssi->cpu_dai_drv.symmetric_samplebits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * Configure TX and RX DMA watermarks -- when to send a DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * Values should be tested to avoid FIFO under/over run. Set maxburst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * to fifo_watermark to maxiumize DMA transaction to reduce overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) switch (ssi->fifo_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * Set to 8 as a balanced configuration -- When TX FIFO has 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * empty slots, send a DMA request to fill these 8 slots. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * remaining 7 slots should be able to allow DMA to finish the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * transaction before TX FIFO underruns; Same applies to RX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * Tested with cases running at 48kHz @ 16 bits x 16 channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ssi->fifo_watermark = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ssi->dma_maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Safely use old watermark configurations for older chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ssi->fifo_watermark = ssi->fifo_depth - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ssi->dma_maxburst = ssi->fifo_depth - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dev_set_drvdata(dev, ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (ssi->soc->imx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) mutex_init(&ssi->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dev_err(dev, "failed to set AC'97 ops\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) goto error_ac97_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) &ssi->cpu_dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dev_err(dev, "failed to register DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) goto error_asoc_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (ssi->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) dev_name(dev), ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) dev_err(dev, "failed to claim irq %u\n", ssi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) goto error_asoc_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* Initially configures SSI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) fsl_ssi_hw_init(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* Register a platform device for older bindings or AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (ssi->card_name[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct device *parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * Do not set SSI dev as the parent of AC97 CODEC device since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * it does not have a DT node. Otherwise ASoC core will assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * CODEC has the same DT node as the SSI, so it may bypass the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * dai_probe() of SSI and then cause NULL DMA data pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (fsl_ssi_is_ac97(ssi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ssi->card_pdev = platform_device_register_data(parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ssi->card_name, ssi->card_idx, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (IS_ERR(ssi->card_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ret = PTR_ERR(ssi->card_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dev_err(dev, "failed to register %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ssi->card_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) goto error_sound_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) error_sound_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) fsl_ssi_debugfs_remove(&ssi->dbg_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) error_asoc_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (fsl_ssi_is_ac97(ssi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) error_ac97_ops:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (fsl_ssi_is_ac97(ssi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) mutex_destroy(&ssi->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (ssi->soc->imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) fsl_ssi_imx_clean(pdev, ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static int fsl_ssi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) fsl_ssi_debugfs_remove(&ssi->dbg_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (ssi->card_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) platform_device_unregister(ssi->card_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* Clean up SSI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) fsl_ssi_hw_clean(ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (ssi->soc->imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) fsl_ssi_imx_clean(pdev, ssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (fsl_ssi_is_ac97(ssi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) mutex_destroy(&ssi->ac97_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static int fsl_ssi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct fsl_ssi *ssi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) regcache_cache_only(regs, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) regcache_mark_dirty(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static int fsl_ssi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct fsl_ssi *ssi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct regmap *regs = ssi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) regcache_cache_only(regs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) regmap_update_bits(regs, REG_SSI_SFCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ssi->regcache_sfcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return regcache_sync(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static const struct dev_pm_ops fsl_ssi_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static struct platform_driver fsl_ssi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .name = "fsl-ssi-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .of_match_table = fsl_ssi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .pm = &fsl_ssi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .probe = fsl_ssi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .remove = fsl_ssi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) module_platform_driver(fsl_ssi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) MODULE_ALIAS("platform:fsl-ssi-dai");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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