Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Nicolin Chen <b42378@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on fsl_ssi.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author: Timur Tabi <timur@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright 2007-2008 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #ifndef _FSL_SPDIF_DAI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define _FSL_SPDIF_DAI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* S/PDIF Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_SPDIF_SCR 			0x0	/* SPDIF Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_SPDIF_SRCD		 	0x4	/* CDText Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_SPDIF_SRPC			0x8	/* PhaseConfig Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_SPDIF_SIE			0xc	/* InterruptEn Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_SPDIF_SIS			0x10	/* InterruptStat Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_SPDIF_SIC			0x10	/* InterruptClear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_SPDIF_SRL			0x14	/* SPDIFRxLeft Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_SPDIF_SRR			0x18	/* SPDIFRxRight Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_SPDIF_SRCSH			0x1c	/* SPDIFRxCChannel_h Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_SPDIF_SRCSL			0x20	/* SPDIFRxCChannel_l Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_SPDIF_SRU			0x24	/* UchannelRx Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_SPDIF_SRQ			0x28	/* QchannelRx Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_SPDIF_STL			0x2C	/* SPDIFTxLeft Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_SPDIF_STR			0x30	/* SPDIFTxRight Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_SPDIF_STCSCH		0x34	/* SPDIFTxCChannelCons_h Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_SPDIF_STCSCL		0x38	/* SPDIFTxCChannelCons_l Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_SPDIF_SRFM			0x44	/* FreqMeas Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_SPDIF_STC			0x50	/* SPDIFTxClk Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* SPDIF Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCR_RXFIFO_CTL_OFFSET		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCR_RXFIFO_CTL_MASK		(1 << SCR_RXFIFO_CTL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCR_RXFIFO_CTL_ZERO		(1 << SCR_RXFIFO_CTL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCR_RXFIFO_OFF_OFFSET		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCR_RXFIFO_OFF_MASK		(1 << SCR_RXFIFO_OFF_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCR_RXFIFO_OFF			(1 << SCR_RXFIFO_OFF_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCR_RXFIFO_RST_OFFSET		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCR_RXFIFO_RST_MASK		(1 << SCR_RXFIFO_RST_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCR_RXFIFO_RST			(1 << SCR_RXFIFO_RST_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCR_RXFIFO_FSEL_OFFSET		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCR_RXFIFO_FSEL_MASK		(0x3 << SCR_RXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCR_RXFIFO_FSEL_IF0		(0x0 << SCR_RXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCR_RXFIFO_FSEL_IF4		(0x1 << SCR_RXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCR_RXFIFO_FSEL_IF8		(0x2 << SCR_RXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCR_RXFIFO_FSEL_IF12		(0x3 << SCR_RXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCR_RXFIFO_AUTOSYNC_OFFSET	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCR_RXFIFO_AUTOSYNC_MASK	(1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCR_RXFIFO_AUTOSYNC		(1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCR_TXFIFO_AUTOSYNC_OFFSET	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCR_TXFIFO_AUTOSYNC_MASK	(1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCR_TXFIFO_AUTOSYNC		(1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCR_TXFIFO_FSEL_OFFSET		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCR_TXFIFO_FSEL_MASK		(0x3 << SCR_TXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCR_TXFIFO_FSEL_IF0		(0x0 << SCR_TXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCR_TXFIFO_FSEL_IF4		(0x1 << SCR_TXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCR_TXFIFO_FSEL_IF8		(0x2 << SCR_TXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCR_TXFIFO_FSEL_IF12		(0x3 << SCR_TXFIFO_FSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCR_LOW_POWER			(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCR_SOFT_RESET			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCR_TXFIFO_CTRL_OFFSET		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCR_TXFIFO_CTRL_MASK		(0x3 << SCR_TXFIFO_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCR_TXFIFO_CTRL_ZERO		(0x0 << SCR_TXFIFO_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCR_TXFIFO_CTRL_NORMAL		(0x1 << SCR_TXFIFO_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCR_TXFIFO_CTRL_ONESAMPLE	(0x2 << SCR_TXFIFO_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCR_DMA_RX_EN_OFFSET		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCR_DMA_RX_EN_MASK		(1 << SCR_DMA_RX_EN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCR_DMA_RX_EN			(1 << SCR_DMA_RX_EN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCR_DMA_TX_EN_OFFSET		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCR_DMA_TX_EN_MASK		(1 << SCR_DMA_TX_EN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCR_DMA_TX_EN			(1 << SCR_DMA_TX_EN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCR_VAL_OFFSET			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SCR_VAL_MASK			(1 << SCR_VAL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SCR_VAL_CLEAR			(1 << SCR_VAL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SCR_TXSEL_OFFSET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SCR_TXSEL_MASK			(0x7 << SCR_TXSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SCR_TXSEL_OFF			(0 << SCR_TXSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SCR_TXSEL_RX			(1 << SCR_TXSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SCR_TXSEL_NORMAL		(0x5 << SCR_TXSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SCR_USRC_SEL_OFFSET		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SCR_USRC_SEL_MASK		(0x3 << SCR_USRC_SEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SCR_USRC_SEL_NONE		(0x0 << SCR_USRC_SEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SCR_USRC_SEL_RECV		(0x1 << SCR_USRC_SEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SCR_USRC_SEL_CHIP		(0x3 << SCR_USRC_SEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SCR_DMA_xX_EN(tx)		(tx ? SCR_DMA_TX_EN : SCR_DMA_RX_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* SPDIF CDText control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SRCD_CD_USER_OFFSET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SRCD_CD_USER			(1 << SRCD_CD_USER_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* SPDIF Phase Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SRPC_DPLL_LOCKED		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SRPC_CLKSRC_SEL_OFFSET		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SRPC_CLKSRC_SEL_MASK		(0xf << SRPC_CLKSRC_SEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SRPC_CLKSRC_SEL_SET(x)		((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SRPC_CLKSRC_SEL_LOCKED_OFFSET1	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SRPC_CLKSRC_SEL_LOCKED_OFFSET2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SRPC_GAINSEL_OFFSET		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SRPC_GAINSEL_MASK		(0x7 << SRPC_GAINSEL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SRPC_GAINSEL_SET(x)		((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SRPC_CLKSRC_MAX			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum spdif_gainsel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	GAINSEL_MULTI_24 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	GAINSEL_MULTI_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	GAINSEL_MULTI_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	GAINSEL_MULTI_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	GAINSEL_MULTI_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	GAINSEL_MULTI_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	GAINSEL_MULTI_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GAINSEL_MULTI_MAX		(GAINSEL_MULTI_3 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SPDIF_DEFAULT_GAINSEL		GAINSEL_MULTI_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* SPDIF interrupt mask define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INT_DPLL_LOCKED			(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INT_TXFIFO_UNOV			(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INT_TXFIFO_RESYNC		(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INT_CNEW			(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define INT_VAL_NOGOOD			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_SYM_ERR			(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INT_BIT_ERR			(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define INT_URX_FUL			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define INT_URX_OV			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INT_QRX_FUL			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define INT_QRX_OV			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define INT_UQ_SYNC			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define INT_UQ_ERR			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define INT_RXFIFO_UNOV			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define INT_RXFIFO_RESYNC		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define INT_LOSS_LOCK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define INT_TX_EM			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define INT_RXFIFO_FUL			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* SPDIF Clock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define STC_SYSCLK_DF_OFFSET		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define STC_SYSCLK_DF_MASK		(0x1ff << STC_SYSCLK_DF_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define STC_SYSCLK_DF(x)		((((x) - 1) << STC_SYSCLK_DF_OFFSET) & STC_SYSCLK_DF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define STC_TXCLK_SRC_OFFSET		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define STC_TXCLK_SRC_MASK		(0x7 << STC_TXCLK_SRC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define STC_TXCLK_SRC_SET(x)		((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define STC_TXCLK_ALL_EN_OFFSET		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STC_TXCLK_ALL_EN_MASK		(1 << STC_TXCLK_ALL_EN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define STC_TXCLK_ALL_EN		(1 << STC_TXCLK_ALL_EN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define STC_TXCLK_DF_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define STC_TXCLK_DF_MASK		(0x7f << STC_TXCLK_DF_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define STC_TXCLK_DF(x)		((((x) - 1) << STC_TXCLK_DF_OFFSET) & STC_TXCLK_DF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define STC_TXCLK_SRC_MAX		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define STC_TXCLK_SPDIF_ROOT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* SPDIF tx rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum spdif_txrate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	SPDIF_TXRATE_32000 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	SPDIF_TXRATE_44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	SPDIF_TXRATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	SPDIF_TXRATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	SPDIF_TXRATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SPDIF_TXRATE_MAX		(SPDIF_TXRATE_192000 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SPDIF_CSTATUS_BYTE		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SPDIF_UBITS_SIZE		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SPDIF_QSUB_SIZE			(SPDIF_UBITS_SIZE / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FSL_SPDIF_RATES_PLAYBACK	(SNDRV_PCM_RATE_32000 |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					 SNDRV_PCM_RATE_44100 |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					 SNDRV_PCM_RATE_48000 |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					 SNDRV_PCM_RATE_96000 |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					 SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FSL_SPDIF_RATES_CAPTURE		(SNDRV_PCM_RATE_16000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					 SNDRV_PCM_RATE_32000 |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					 SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					 SNDRV_PCM_RATE_48000 |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					 SNDRV_PCM_RATE_64000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					 SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FSL_SPDIF_FORMATS_PLAYBACK	(SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					 SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					 SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FSL_SPDIF_FORMATS_CAPTURE	(SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* _FSL_SPDIF_DAI_H */