^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Based on stmp3xxx_spdif_dai.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Vladimir Barinov <vbarinov@embeddedalley.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Copyright 2008 SigmaTel, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Copyright 2008 Embedded Alley Solutions, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitrev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "fsl_spdif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSL_SPDIF_TXFIFO_WML 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FSL_SPDIF_RXFIFO_WML 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) INT_LOSS_LOCK | INT_DPLL_LOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Index list for the values that has if (DPLL Locked) condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRPC_NODPLL_START1 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRPC_NODPLL_START2 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DEFAULT_RXCLK_SRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct fsl_spdif_soc_data: soc specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @imx: for imx platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @shared_root_clock: flag of sharing a clock source with others;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * so the driver shouldn't set root clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct fsl_spdif_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool shared_root_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * SPDIF control structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Defines channel status, subcode and Q sub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct spdif_mixer_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* spinlock to access control data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) spinlock_t ctl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* IEC958 channel tx status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned char ch_status[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* User bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned char subcode[2 * SPDIF_UBITS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Q subcode part of user bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned char qsub[2 * SPDIF_QSUB_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Buffer offset for U/Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 upos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 qpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Ready buffer index of the two buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 ready_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * struct fsl_spdif_priv - Freescale SPDIF private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @soc: SPDIF soc data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @fsl_spdif_control: SPDIF control data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @cpu_dai_drv: cpu dai driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @pdev: platform device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @regmap: regmap handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @dpll_locked: dpll lock flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @txrate: the best rates for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @txclk_df: STC_TXCLK_DF dividers value for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @sysclk_df: STC_SYSCLK_DF dividers value for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @txclk_src: STC_TXCLK_SRC values for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @rxclk_src: SRPC_CLKSRC_SEL values for capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @txclk: tx clock sources for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @rxclk: rx clock sources for capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @coreclk: core clock for register access via DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @sysclk: system clock for rx clock rate measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @spbaclk: SPBA clock (optional, depending on SoC design)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @dma_params_tx: DMA parameters for transmit channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @dma_params_rx: DMA parameters for receive channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @regcache_srpc: regcache for SRPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct fsl_spdif_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct fsl_spdif_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct spdif_mixer_control fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct snd_soc_dai_driver cpu_dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bool dpll_locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 txrate[SPDIF_TXRATE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 txclk_df[SPDIF_TXRATE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 sysclk_df[SPDIF_TXRATE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 txclk_src[SPDIF_TXRATE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 rxclk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk *txclk[SPDIF_TXRATE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *rxclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk *coreclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clk *sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk *spbaclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct snd_dmaengine_dai_dma_data dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* regcache for SRPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 regcache_srpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .imx = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .shared_root_clock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .imx = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .shared_root_clock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .imx = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .shared_root_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Check if clk is a root clock that does not share clock source with others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* DPLL locked and lock loss interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) regmap_read(regmap, REG_SPDIF_SRPC, &locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) locked &= SRPC_DPLL_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) locked ? "locked" : "loss lock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spdif_priv->dpll_locked = locked ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Receiver found illegal symbol interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Clear illegal symbol if DPLL unlocked since no audio stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!spdif_priv->dpll_locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* U/Q Channel receive register full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 *pos, size, val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) switch (name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case 'U':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pos = &ctrl->upos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) size = SPDIF_UBITS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) reg = REG_SPDIF_SRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case 'Q':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pos = &ctrl->qpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size = SPDIF_QSUB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg = REG_SPDIF_SRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(&pdev->dev, "unsupported channel name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (*pos >= size * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else if (unlikely((*pos % size) + 3 > size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(&pdev->dev, "User bit receive buffer overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_read(regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ctrl->subcode[*pos++] = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ctrl->subcode[*pos++] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ctrl->subcode[*pos++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* U/Q Channel sync found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* U/Q buffer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ctrl->qpos == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Set ready to this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* U/Q Channel framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Read U/Q data to clear the irq and do buffer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) regmap_read(regmap, REG_SPDIF_SRU, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) regmap_read(regmap, REG_SPDIF_SRQ, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Drop this U/Q buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ctrl->ready_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ctrl->upos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ctrl->qpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Get spdif interrupt status and clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 val, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_read(regmap, REG_SPDIF_SIS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regmap_read(regmap, REG_SPDIF_SIE, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_write(regmap, REG_SPDIF_SIC, val & val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static irqreturn_t spdif_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 sis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sis = spdif_intr_status_clear(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (sis & INT_DPLL_LOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spdif_irq_dpll_lock(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (sis & INT_TXFIFO_UNOV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (sis & INT_TXFIFO_RESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (sis & INT_CNEW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_dbg(&pdev->dev, "isr: cstatus new\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (sis & INT_VAL_NOGOOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_dbg(&pdev->dev, "isr: validity flag no good\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (sis & INT_SYM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spdif_irq_sym_error(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (sis & INT_BIT_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (sis & INT_URX_FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spdif_irq_uqrx_full(spdif_priv, 'U');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (sis & INT_URX_OV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (sis & INT_QRX_FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) spdif_irq_uqrx_full(spdif_priv, 'Q');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (sis & INT_QRX_OV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (sis & INT_UQ_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spdif_irq_uq_sync(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (sis & INT_UQ_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spdif_irq_uq_err(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (sis & INT_RXFIFO_UNOV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (sis & INT_RXFIFO_RESYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (sis & INT_LOSS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) spdif_irq_dpll_lock(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* FIXME: Write Tx FIFO to clear TxEm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (sis & INT_TX_EM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* FIXME: Read Rx FIFO to clear RxFIFOFul */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (sis & INT_RXFIFO_FUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 val, cycle = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regcache_cache_bypass(regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * RESET bit would be cleared after finishing its reset procedure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * which typically lasts 8 cycles. 1000 cycles will keep it safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regmap_read(regmap, REG_SPDIF_SCR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } while ((val & SCR_SOFT_RESET) && cycle--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) regcache_cache_bypass(regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) regcache_mark_dirty(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regcache_sync(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 mask, u8 cstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ctrl->ch_status[3] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ctrl->ch_status[3] |= cstatus & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 ch_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (bitrev8(ctrl->ch_status[1]) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bitrev8(ctrl->ch_status[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ch_status = bitrev8(ctrl->ch_status[3]) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Set SPDIF PhaseConfig register for rx clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum spdif_gainsel gainsel, int dpll_locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u8 clksrc = spdif_priv->rxclk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regmap_update_bits(regmap, REG_SPDIF_SRPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long csfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 stc, mask, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u16 sysclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u8 clk, txclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (sample_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rate = SPDIF_TXRATE_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) csfs = IEC958_AES3_CON_FS_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) rate = SPDIF_TXRATE_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) csfs = IEC958_AES3_CON_FS_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rate = SPDIF_TXRATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) csfs = IEC958_AES3_CON_FS_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rate = SPDIF_TXRATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) csfs = IEC958_AES3_CON_FS_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rate = SPDIF_TXRATE_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) csfs = IEC958_AES3_CON_FS_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) clk = spdif_priv->txclk_src[rate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (clk >= STC_TXCLK_SRC_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(&pdev->dev, "tx clock source is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) txclk_df = spdif_priv->txclk_df[rate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (txclk_df == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(&pdev->dev, "the txclk_df can't be zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sysclk_df = spdif_priv->sysclk_df[rate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto clk_set_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = clk_set_rate(spdif_priv->txclk[rate],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 64 * sample_rate * txclk_df);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(&pdev->dev, "failed to set tx clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clk_set_bypass:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_dbg(&pdev->dev, "expected clock rate = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) (64 * sample_rate * txclk_df * sysclk_df));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clk_get_rate(spdif_priv->txclk[rate]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* set fs field in consumer channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* select clock source and divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spdif_priv->txrate[rate], sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int fsl_spdif_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 scr, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Reset module and interrupts only for first initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!snd_soc_dai_active(cpu_dai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = spdif_softreset(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(&pdev->dev, "failed to soft reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Disable all the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SCR_TXFIFO_FSEL_IF8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SCR_TXFIFO_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Power up SPDIF module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 scr, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) scr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) SCR_TXFIFO_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Disable TX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Power down SPDIF module only if tx&rx are both inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!snd_soc_dai_active(cpu_dai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) spdif_intr_status_clear(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) regmap_update_bits(regmap, REG_SPDIF_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SCR_LOW_POWER, SCR_LOW_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 sample_rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = spdif_set_sample_rate(substream, sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) __func__, sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) IEC958_AES3_CON_CLOCK_1000PPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spdif_write_channel_status(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Setup rx clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 intr = SIE_INTR_FOR(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 dmaen = SCR_DMA_xX_EN(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .startup = fsl_spdif_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .hw_params = fsl_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .trigger = fsl_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .shutdown = fsl_spdif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * FSL SPDIF IEC958 controller(mixer) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Channel status get/put control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * User bit value get/put control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * Valid bit value get control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * DPLL lock status get control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * User bit sync mode selection control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) uvalue->value.iec958.status[0] = ctrl->ch_status[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) uvalue->value.iec958.status[1] = ctrl->ch_status[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) uvalue->value.iec958.status[2] = ctrl->ch_status[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) uvalue->value.iec958.status[3] = ctrl->ch_status[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct snd_ctl_elem_value *uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ctrl->ch_status[0] = uvalue->value.iec958.status[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ctrl->ch_status[1] = uvalue->value.iec958.status[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ctrl->ch_status[2] = uvalue->value.iec958.status[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ctrl->ch_status[3] = uvalue->value.iec958.status[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spdif_write_channel_status(spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Get channel status from SPDIF_RX_CCHAN register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 cstatus, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_read(regmap, REG_SPDIF_SIS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!(val & INT_CNEW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ucontrol->value.iec958.status[2] = cstatus & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ucontrol->value.iec958.status[5] = cstatus & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Clear intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Get User bits (subcode) from chip value which readed out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * in UChannel register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock_irqsave(&ctrl->ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ctrl->ready_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) memcpy(&ucontrol->value.iec958.subcode[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uinfo->count = SPDIF_QSUB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Get Q subcode from chip value which readed out in QChannel register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_lock_irqsave(&ctrl->ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ctrl->ready_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) memcpy(&ucontrol->value.bytes.data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Valid bit information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Get valid good bit from interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) regmap_read(regmap, REG_SPDIF_SIS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) regmap_read(regmap, REG_SPDIF_SCR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) val = 1 - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* DPLL lock information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) uinfo->value.integer.min = 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uinfo->value.integer.max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 24, 16, 12, 8, 6, 4, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Get RX data clock rate given the SPDIF bus_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) enum spdif_gainsel gainsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u64 tmpval64, busclk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u32 freqmeas, phaseconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u8 clksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Get bus clock from system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) busclk_freq = clk_get_rate(spdif_priv->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) tmpval64 = (u64) busclk_freq * freqmeas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) do_div(tmpval64, gainsel_multi[gainsel] * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) do_div(tmpval64, 128 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return (int)tmpval64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Get DPLL lock or not info from stable interrupt status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * User application must use this control to get locked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * then can do next PCM operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (spdif_priv->dpll_locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ucontrol->value.integer.value[0] = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* User bit sync mode info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * User bit sync mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * 1 CD User channel subcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * 0 Non-CD data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) regmap_read(regmap, REG_SPDIF_SRCD, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * User bit sync mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * 1 CD User channel subcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * 0 Non-CD data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct regmap *regmap = spdif_priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* FSL SPDIF IEC958 controller defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Status cchanel controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) SNDRV_CTL_ELEM_ACCESS_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .info = fsl_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .get = fsl_spdif_pb_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .put = fsl_spdif_pb_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .info = fsl_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .get = fsl_spdif_capture_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* User bits controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .name = "IEC958 Subcode Capture Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .info = fsl_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .get = fsl_spdif_subcode_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .name = "IEC958 Q-subcode Capture Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .info = fsl_spdif_qinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .get = fsl_spdif_qget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Valid bit error controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .name = "IEC958 RX V-Bit Errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .info = fsl_spdif_vbit_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .get = fsl_spdif_rx_vbit_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .name = "IEC958 TX V-Bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SNDRV_CTL_ELEM_ACCESS_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .info = fsl_spdif_vbit_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .get = fsl_spdif_tx_vbit_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .put = fsl_spdif_tx_vbit_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* DPLL lock info get controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .name = "RX Sample Rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .info = fsl_spdif_rxrate_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .get = fsl_spdif_rxrate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* User bit sync mode set/get controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .name = "IEC958 USyncMode CDText",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) SNDRV_CTL_ELEM_ACCESS_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .info = fsl_spdif_usync_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .get = fsl_spdif_usync_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .put = fsl_spdif_usync_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) &spdif_private->dma_params_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*Clear the val bit for Tx*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SCR_VAL_MASK, SCR_VAL_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static struct snd_soc_dai_driver fsl_spdif_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .probe = &fsl_spdif_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .stream_name = "CPU-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .rates = FSL_SPDIF_RATES_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .formats = FSL_SPDIF_FORMATS_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .stream_name = "CPU-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .rates = FSL_SPDIF_RATES_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .formats = FSL_SPDIF_FORMATS_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .ops = &fsl_spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const struct snd_soc_component_driver fsl_spdif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .name = "fsl-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* FSL SPDIF REGMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const struct reg_default fsl_spdif_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {REG_SPDIF_SCR, 0x00000400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {REG_SPDIF_SRCD, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {REG_SPDIF_SIE, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {REG_SPDIF_STL, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {REG_SPDIF_STR, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {REG_SPDIF_STCSCH, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {REG_SPDIF_STCSCL, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {REG_SPDIF_STC, 0x00020f00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case REG_SPDIF_SCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case REG_SPDIF_SRCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case REG_SPDIF_SRPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case REG_SPDIF_SIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case REG_SPDIF_SIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case REG_SPDIF_SRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case REG_SPDIF_SRR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case REG_SPDIF_SRCSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case REG_SPDIF_SRCSL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case REG_SPDIF_SRU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case REG_SPDIF_SRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case REG_SPDIF_STCSCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case REG_SPDIF_STCSCL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) case REG_SPDIF_SRFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case REG_SPDIF_STC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case REG_SPDIF_SRPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case REG_SPDIF_SIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case REG_SPDIF_SRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case REG_SPDIF_SRR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case REG_SPDIF_SRCSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case REG_SPDIF_SRCSL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case REG_SPDIF_SRU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case REG_SPDIF_SRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case REG_SPDIF_SRFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) case REG_SPDIF_SCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case REG_SPDIF_SRCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case REG_SPDIF_SRPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case REG_SPDIF_SIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case REG_SPDIF_SIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case REG_SPDIF_STL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case REG_SPDIF_STR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) case REG_SPDIF_STCSCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case REG_SPDIF_STCSCL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case REG_SPDIF_STC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const struct regmap_config fsl_spdif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .max_register = REG_SPDIF_STC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .reg_defaults = fsl_spdif_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .readable_reg = fsl_spdif_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .volatile_reg = fsl_spdif_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .writeable_reg = fsl_spdif_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct clk *clk, u64 savesub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) enum spdif_txrate index, bool round)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u64 rate_ideal, rate_actual, sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 arate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u8 txclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* The sysclk has an extra divisor [2, 512] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) sysclk_dfmin = is_sysclk ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) sysclk_dfmax = is_sysclk ? 512 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) rate_ideal = rate[index] * txclk_df * 64ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (round)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) rate_actual = clk_round_rate(clk, rate_ideal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rate_actual = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) arate = rate_actual / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) arate /= txclk_df * sysclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (arate == rate[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* We are lucky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) savesub = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) spdif_priv->txclk_df[index] = txclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) spdif_priv->sysclk_df[index] = sysclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) spdif_priv->txrate[index] = arate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) } else if (arate / rate[index] == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* A little bigger than expect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) sub = (u64)(arate - rate[index]) * 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) do_div(sub, rate[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (sub >= savesub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) savesub = sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) spdif_priv->txclk_df[index] = txclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) spdif_priv->sysclk_df[index] = sysclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) spdif_priv->txrate[index] = arate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) } else if (rate[index] / arate == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* A little smaller than expect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) sub = (u64)(rate[index] - arate) * 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) do_div(sub, rate[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (sub >= savesub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) savesub = sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) spdif_priv->txclk_df[index] = txclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spdif_priv->sysclk_df[index] = sysclk_df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) spdif_priv->txrate[index] = arate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return savesub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) enum spdif_txrate index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct platform_device *pdev = spdif_priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u64 savesub = 100000, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) char tmp[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) sprintf(tmp, "rxtx%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) clk = devm_clk_get(&pdev->dev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(dev, "no rxtx%d clock in devicetree\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (!clk_get_rate(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) fsl_spdif_can_set_clk_rate(spdif_priv, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (savesub == ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) savesub = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) spdif_priv->txclk[index] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) spdif_priv->txclk_src[index] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* To quick catch a divisor, we allow a 0.1% deviation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (savesub < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) spdif_priv->txclk_src[index], rate[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) spdif_priv->txclk_df[index], rate[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) spdif_priv->sysclk_df[index], rate[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) rate[index], spdif_priv->txrate[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int fsl_spdif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct fsl_spdif_priv *spdif_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct spdif_mixer_control *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int irq, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (!spdif_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) spdif_priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) spdif_priv->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!spdif_priv->soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dev_err(&pdev->dev, "failed to get soc data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* Initialize this copy of the CPU DAI driver structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Get the addresses and IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "core", regs, &fsl_spdif_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (IS_ERR(spdif_priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return PTR_ERR(spdif_priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_name(&pdev->dev), spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dev_err(&pdev->dev, "could not claim irq %u\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Get system clock for rx clock rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (IS_ERR(spdif_priv->sysclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return PTR_ERR(spdif_priv->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* Get core clock for data register access via DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (IS_ERR(spdif_priv->coreclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_err(&pdev->dev, "no core clock in devicetree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return PTR_ERR(spdif_priv->coreclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (IS_ERR(spdif_priv->spbaclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_warn(&pdev->dev, "no spba clock in devicetree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* Select clock source for rx/tx clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (IS_ERR(spdif_priv->rxclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return PTR_ERR(spdif_priv->rxclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret = fsl_spdif_probe_txclk(spdif_priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Initial spinlock for control data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ctrl = &spdif_priv->fsl_spdif_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) spin_lock_init(&ctrl->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* Init tx channel status default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) IEC958_AES0_CON_EMPHASIS_5015;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ctrl->ch_status[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) IEC958_AES3_CON_CLOCK_1000PPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) spdif_priv->dpll_locked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* Register with ASoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_set_drvdata(&pdev->dev, spdif_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) regcache_cache_only(spdif_priv->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) &spdif_priv->cpu_dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static int fsl_spdif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static int fsl_spdif_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* Disable all the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) &spdif_priv->regcache_srpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) regcache_cache_only(spdif_priv->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) clk_disable_unprepare(spdif_priv->rxclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) for (i = 0; i < SPDIF_TXRATE_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) clk_disable_unprepare(spdif_priv->txclk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (!IS_ERR(spdif_priv->spbaclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) clk_disable_unprepare(spdif_priv->spbaclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) clk_disable_unprepare(spdif_priv->coreclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int fsl_spdif_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = clk_prepare_enable(spdif_priv->coreclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_err(dev, "failed to enable core clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (!IS_ERR(spdif_priv->spbaclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ret = clk_prepare_enable(spdif_priv->spbaclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(dev, "failed to enable spba clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) goto disable_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret = clk_prepare_enable(spdif_priv->txclk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) goto disable_tx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = clk_prepare_enable(spdif_priv->rxclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) goto disable_tx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) regcache_cache_only(spdif_priv->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) regcache_mark_dirty(spdif_priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) spdif_priv->regcache_srpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ret = regcache_sync(spdif_priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) goto disable_rx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) disable_rx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) clk_disable_unprepare(spdif_priv->rxclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) disable_tx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) for (i--; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) clk_disable_unprepare(spdif_priv->txclk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (!IS_ERR(spdif_priv->spbaclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) clk_disable_unprepare(spdif_priv->spbaclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) disable_core_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) clk_disable_unprepare(spdif_priv->coreclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static const struct dev_pm_ops fsl_spdif_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static const struct of_device_id fsl_spdif_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static struct platform_driver fsl_spdif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .name = "fsl-spdif-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .of_match_table = fsl_spdif_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .pm = &fsl_spdif_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .probe = fsl_spdif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .remove = fsl_spdif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) module_platform_driver(fsl_spdif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) MODULE_ALIAS("platform:fsl-spdif-dai");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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