^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012-2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __FSL_SAI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __FSL_SAI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) SNDRV_PCM_FMTBIT_S20_3LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* SAI Register Map Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FSL_SAI_VERID 0x00 /* SAI Version ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FSL_SAI_xDR(tx, ofs) (tx ? FSL_SAI_TDR(ofs) : FSL_SAI_RDR(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FSL_SAI_xFR(tx, ofs) (tx ? FSL_SAI_TFR(ofs) : FSL_SAI_RFR(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* SAI Transmit/Receive Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FSL_SAI_CSR_TERE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FSL_SAI_CSR_SE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FSL_SAI_CSR_FR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FSL_SAI_CSR_SR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FSL_SAI_CSR_xF_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FSL_SAI_CSR_xF_W_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FSL_SAI_CSR_WSF BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FSL_SAI_CSR_SEF BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FSL_SAI_CSR_FEF BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FSL_SAI_CSR_FWF BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FSL_SAI_CSR_FRF BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FSL_SAI_CSR_xIE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FSL_SAI_CSR_WSIE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FSL_SAI_CSR_SEIE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FSL_SAI_CSR_FEIE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FSL_SAI_CSR_FWIE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FSL_SAI_CSR_FRIE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FSL_SAI_CSR_FRDE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* SAI Transmit and Receive Configuration 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* SAI Transmit and Receive Configuration 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FSL_SAI_CR2_SYNC BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FSL_SAI_CR2_MSEL_BUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FSL_SAI_CR2_BCP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FSL_SAI_CR2_BCD_MSTR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FSL_SAI_CR2_DIV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* SAI Transmit and Receive Configuration 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FSL_SAI_CR3_TRCE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FSL_SAI_CR3_WDFL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FSL_SAI_CR3_WDFL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* SAI Transmit and Receive Configuration 4 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FSL_SAI_CR4_FCONT BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FSL_SAI_CR4_FCOMB_SOFT BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FSL_SAI_CR4_FPACK_8 (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FSL_SAI_CR4_FPACK_16 (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FSL_SAI_CR4_CHMOD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FSL_SAI_CR4_CHMOD_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FSL_SAI_CR4_MF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FSL_SAI_CR4_FSE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FSL_SAI_CR4_FSP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FSL_SAI_CR4_FSD_MSTR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* SAI Transmit and Receive Configuration 5 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FSL_SAI_CR5_FBT(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* SAI MCLK Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FSL_SAI_MCTL_MSEL_BUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FSL_SAI_MCTL_DIV_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FSL_SAI_MCTL_DIV_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* SAI VERID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FSL_SAI_VERID_MAJOR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FSL_SAI_VERID_MINOR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FSL_SAI_VERID_FEATURE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FSL_SAI_VERID_EFIFO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FSL_SAI_VERID_TSTMP_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* SAI PARAM Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FSL_SAI_PARAM_SPF_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FSL_SAI_PARAM_WPF_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SAI MCLK Divide Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FSL_SAI_MDIV_MASK 0xFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* SAI timestamp and bitcounter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FSL_SAI_xTCTL_TSEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FSL_SAI_xTCTL_TSINC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FSL_SAI_xTCTL_RTSC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FSL_SAI_xTCTL_RBC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* SAI type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FSL_SAI_DMA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FSL_SAI_USE_AC97 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FSL_SAI_NET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FSL_SAI_TRA_SYN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FSL_SAI_REC_SYN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FSL_SAI_USE_I2S_SLAVE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FSL_FMT_TRANSMITTER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FSL_FMT_RECEIVER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* SAI clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define FSL_SAI_CLK_BUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define FSL_SAI_CLK_MAST1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define FSL_SAI_CLK_MAST2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FSL_SAI_CLK_MAST3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define FSL_SAI_MCLK_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* SAI data transfer numbers per DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define FSL_SAI_MAXBURST_TX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define FSL_SAI_MAXBURST_RX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct fsl_sai_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bool use_imx_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool use_edma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * struct fsl_sai_verid - version id data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @major: major version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @minor: minor version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @feature: feature specification number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 0000000000000000b - Standard feature set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 0000000000000000b - Standard feature set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct fsl_sai_verid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * struct fsl_sai_param - parameter data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @slot_num: The maximum number of slots per frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @fifo_depth: The number of words in each FIFO (depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @dataline: The number of datalines implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct fsl_sai_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 dataline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct fsl_sai {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bool is_slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bool is_lsb_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bool is_dsp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bool synchronous[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int mclk_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int mclk_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int bclk_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct fsl_sai_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct snd_soc_dai_driver cpu_dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_dmaengine_dai_dma_data dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct fsl_sai_verid verid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct fsl_sai_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif /* __FSL_SAI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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