^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2012-2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "fsl_sai.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FSL_SAI_CSR_FEIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const unsigned int fsl_sai_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 8000, 11025, 12000, 16000, 22050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 24000, 32000, 44100, 48000, 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 88200, 96000, 176400, 192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .count = ARRAY_SIZE(fsl_sai_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .list = fsl_sai_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * or Receiver's for both streams. This function is used to check if clocks of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * the stream's are synced by the opposite stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @sai: SAI context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @dir: stream direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int adir = (dir == TX) ? RX : TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* current dir in async mode while opposite dir in sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return !sai->synchronous[dir] && sai->synchronous[adir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static irqreturn_t fsl_sai_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct fsl_sai *sai = (struct fsl_sai *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev = &sai->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 flags, xcsr, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool irq_none = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Both IRQ status bits and IRQ mask bits are in the xCSR but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * different shifts. And we here create a mask only for those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * IRQs that we activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Tx IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) flags = xcsr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) irq_none = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) goto irq_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (flags & FSL_SAI_CSR_WSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_dbg(dev, "isr: Start of Tx word detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (flags & FSL_SAI_CSR_SEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_dbg(dev, "isr: Tx Frame sync error detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (flags & FSL_SAI_CSR_FEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_dbg(dev, "isr: Transmit underrun detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* FIFO reset for safety */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) xcsr |= FSL_SAI_CSR_FR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (flags & FSL_SAI_CSR_FWF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (flags & FSL_SAI_CSR_FRF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) flags &= FSL_SAI_CSR_xF_W_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) xcsr &= ~FSL_SAI_CSR_xF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) irq_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Rx IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) flags = xcsr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) irq_none = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (flags & FSL_SAI_CSR_WSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_dbg(dev, "isr: Start of Rx word detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (flags & FSL_SAI_CSR_SEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_dbg(dev, "isr: Rx Frame sync error detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (flags & FSL_SAI_CSR_FEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(dev, "isr: Receive overflow detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* FIFO reset for safety */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) xcsr |= FSL_SAI_CSR_FR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (flags & FSL_SAI_CSR_FWF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (flags & FSL_SAI_CSR_FRF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) flags &= FSL_SAI_CSR_xF_W_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) xcsr &= ~FSL_SAI_CSR_xF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (irq_none)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 rx_mask, int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sai->slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sai->slot_width = slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sai->bclk_ratio = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int clk_id, unsigned int freq, int fsl_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 val_cr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case FSL_SAI_CLK_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case FSL_SAI_CLK_MAST1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case FSL_SAI_CLK_MAST2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case FSL_SAI_CLK_MAST3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FSL_SAI_CR2_MSEL_MASK, val_cr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (dir == SND_SOC_CLOCK_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FSL_FMT_TRANSMITTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FSL_FMT_RECEIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int fmt, int fsl_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 val_cr2 = 0, val_cr4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!sai->is_lsb_first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val_cr4 |= FSL_SAI_CR4_MF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* DAI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Frame low, 1clk before data, one word length for frame sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * frame sync starts one serial clock cycle earlier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * that is, together with the last bit of the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * data word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val_cr2 |= FSL_SAI_CR2_BCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Frame high, one word length for frame sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * frame sync asserts with the first bit of the frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val_cr2 |= FSL_SAI_CR2_BCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Frame high, 1clk before data, one bit for frame sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * frame sync starts one serial clock cycle earlier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * that is, together with the last bit of the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * data word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val_cr2 |= FSL_SAI_CR2_BCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val_cr4 |= FSL_SAI_CR4_FSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sai->is_dsp_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Frame high, one bit for frame sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * frame sync asserts with the first bit of the frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val_cr2 |= FSL_SAI_CR2_BCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sai->is_dsp_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* To be done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* DAI clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Invert both clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val_cr2 ^= FSL_SAI_CR2_BCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val_cr4 ^= FSL_SAI_CR4_FSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Invert bit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val_cr2 ^= FSL_SAI_CR2_BCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Invert frame clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) val_cr4 ^= FSL_SAI_CR4_FSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Nothing to do for both normal cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* DAI clock master masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sai->is_slave_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sai->is_slave_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) sai->is_slave_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sai->is_slave_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 savediv = 0, ratio, savesub = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int adir = tx ? RX : TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int dir = tx ? TX : RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Don't apply to slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (sai->is_slave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_rate = clk_get_rate(sai->mclk_clk[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ratio = clk_rate / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = clk_rate - ratio * freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Drop the source that can not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * divided into the required rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret != 0 && clk_rate / ret < 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_dbg(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "ratio %d for freq %dHz based on clock %ldHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ratio, freq, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ratio /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret < savesub) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) savediv = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sai->mclk_id[tx] = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) savesub = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (savediv == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tx ? 'T' : 'R', freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * 1) For Asynchronous mode, we must set RCR2 register for capture, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * set TCR2 register for playback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * and capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * and capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * 4) For Tx and Rx are both Synchronous with another SAI, we just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (fsl_sai_dir_is_synced(sai, adir)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FSL_SAI_CR2_MSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FSL_SAI_CR2_DIV_MASK, savediv - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else if (!sai->synchronous[dir]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) FSL_SAI_CR2_MSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FSL_SAI_CR2_DIV_MASK, savediv - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sai->mclk_id[tx], savediv, savesub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 word_width = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 val_cr4 = 0, val_cr5 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 slots = (channels == 1) ? 2 : channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 slot_width = word_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int adir = tx ? RX : TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (sai->slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) slots = sai->slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (sai->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) slot_width = sai->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pins = DIV_ROUND_UP(channels, slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!sai->is_slave_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (sai->bclk_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = fsl_sai_set_bclk(cpu_dai, tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sai->bclk_ratio *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = fsl_sai_set_bclk(cpu_dai, tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) slots * slot_width *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Do not enable the clock if it is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!(sai->mclk_streams & BIT(substream->stream))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sai->mclk_streams |= BIT(substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!sai->is_dsp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (sai->is_lsb_first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) val_cr5 |= FSL_SAI_CR5_FBT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Set to output mode to avoid tri-stated data pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val_cr4 |= FSL_SAI_CR4_CHMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * RCR5(TCR5) for playback(capture), or there will be sync error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) FSL_SAI_CR4_CHMOD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) val_cr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) FSL_SAI_CR5_FBT_MASK, val_cr5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) FSL_SAI_CR3_TRCE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) FSL_SAI_CR3_TRCE((1 << pins) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) FSL_SAI_CR4_CHMOD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) val_cr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) FSL_SAI_CR5_FBT_MASK, val_cr5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) regmap_write(sai->regmap, FSL_SAI_xMR(tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ~0UL - ((1 << min(channels, slots)) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) FSL_SAI_CR3_TRCE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!sai->is_slave_mode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sai->mclk_streams & BIT(substream->stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sai->mclk_streams &= ~BIT(substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool tx = dir == TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 xcsr, count = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) FSL_SAI_CSR_TERE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* TERE will remain set till the end of current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } while (--count && xcsr & FSL_SAI_CSR_TERE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * For sai master mode, after several open/close sai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * there will be no frame clock, and can't recover
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * anymore. Add software reset to fix this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * This is a hardware bug, and will be fix in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * next sai version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!sai->is_slave_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Clear SR bit to finish the reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int adir = tx ? RX : TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int dir = tx ? TX : RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 xcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Asynchronous mode: Clear SYNC for both Tx and Rx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * It is recommended that the transmitter is the last enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * and the first disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Enable the opposite direction for synchronous mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * RM recommends to enable RE after TE for case 1 and to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * TE after RE for case 2, but we here may not always guarantee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * TE after RE, which is against what RM recommends but should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * be safe to do, judging by years of testing results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (fsl_sai_dir_is_synced(sai, adir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) FSL_SAI_CSR_FRDE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) FSL_SAI_CSR_xIE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Check if the opposite FRDE is also disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * If opposite stream provides clocks for synchronous mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * it is inactive, disable it before disabling the current one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) fsl_sai_config_disable(sai, adir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Disable current stream if either of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * 1. current stream doesn't provide clocks for synchronous mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * 2. current stream provides clocks for synchronous mode but no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * more stream is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fsl_sai_config_disable(sai, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int fsl_sai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * EDMA controller needs period size to be a multiple of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * tx/rx maxburst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (sai->soc_data->use_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) snd_pcm_hw_constraint_step(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tx ? sai->dma_params_tx.maxburst :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) sai->dma_params_rx.maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .set_sysclk = fsl_sai_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .set_fmt = fsl_sai_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .hw_params = fsl_sai_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .hw_free = fsl_sai_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .trigger = fsl_sai_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .startup = fsl_sai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Software Reset for both Tx and Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Clear SR bit to finish the reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) FSL_SAI_MAXBURST_RX - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &sai->dma_params_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) snd_soc_dai_set_drvdata(cpu_dai, sai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct snd_soc_dai_driver fsl_sai_dai_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .probe = fsl_sai_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .stream_name = "CPU-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .formats = FSL_SAI_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .stream_name = "CPU-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .formats = FSL_SAI_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .ops = &fsl_sai_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const struct snd_soc_component_driver fsl_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .name = "fsl-sai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {FSL_SAI_TCR1(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {FSL_SAI_TCR2(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {FSL_SAI_TCR3(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {FSL_SAI_TCR4(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {FSL_SAI_TCR5(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {FSL_SAI_TDR0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {FSL_SAI_TDR1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {FSL_SAI_TDR2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {FSL_SAI_TDR3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {FSL_SAI_TDR4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {FSL_SAI_TDR5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {FSL_SAI_TDR6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {FSL_SAI_TDR7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {FSL_SAI_TMR, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {FSL_SAI_RCR1(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {FSL_SAI_RCR2(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {FSL_SAI_RCR3(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {FSL_SAI_RCR4(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {FSL_SAI_RCR5(0), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {FSL_SAI_RMR, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {FSL_SAI_TCR1(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {FSL_SAI_TCR2(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {FSL_SAI_TCR3(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {FSL_SAI_TCR4(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {FSL_SAI_TCR5(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {FSL_SAI_TDR0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {FSL_SAI_TDR1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {FSL_SAI_TDR2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {FSL_SAI_TDR3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {FSL_SAI_TDR4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {FSL_SAI_TDR5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {FSL_SAI_TDR6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {FSL_SAI_TDR7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {FSL_SAI_TMR, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {FSL_SAI_RCR1(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {FSL_SAI_RCR2(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {FSL_SAI_RCR3(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {FSL_SAI_RCR4(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {FSL_SAI_RCR5(8), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {FSL_SAI_RMR, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {FSL_SAI_MCTL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {FSL_SAI_MDIV, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct fsl_sai *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case FSL_SAI_TFR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case FSL_SAI_TFR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case FSL_SAI_TFR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case FSL_SAI_TFR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case FSL_SAI_TFR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case FSL_SAI_TFR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case FSL_SAI_TFR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case FSL_SAI_TFR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case FSL_SAI_TMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case FSL_SAI_RDR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case FSL_SAI_RDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case FSL_SAI_RDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case FSL_SAI_RDR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case FSL_SAI_RDR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case FSL_SAI_RDR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case FSL_SAI_RDR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case FSL_SAI_RDR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case FSL_SAI_RFR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case FSL_SAI_RFR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case FSL_SAI_RFR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case FSL_SAI_RFR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case FSL_SAI_RFR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case FSL_SAI_RFR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case FSL_SAI_RFR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case FSL_SAI_RFR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case FSL_SAI_RMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case FSL_SAI_MCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case FSL_SAI_MDIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case FSL_SAI_VERID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case FSL_SAI_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case FSL_SAI_TTCTN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case FSL_SAI_RTCTN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case FSL_SAI_TTCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case FSL_SAI_TBCTN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case FSL_SAI_TTCAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case FSL_SAI_RTCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case FSL_SAI_RBCTN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case FSL_SAI_RTCAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct fsl_sai *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Set VERID and PARAM be volatile for reading value in probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case FSL_SAI_TFR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case FSL_SAI_TFR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case FSL_SAI_TFR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case FSL_SAI_TFR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case FSL_SAI_TFR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case FSL_SAI_TFR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case FSL_SAI_TFR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case FSL_SAI_TFR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case FSL_SAI_RFR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case FSL_SAI_RFR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case FSL_SAI_RFR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case FSL_SAI_RFR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case FSL_SAI_RFR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case FSL_SAI_RFR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case FSL_SAI_RFR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case FSL_SAI_RFR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case FSL_SAI_RDR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case FSL_SAI_RDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case FSL_SAI_RDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case FSL_SAI_RDR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case FSL_SAI_RDR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case FSL_SAI_RDR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case FSL_SAI_RDR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case FSL_SAI_RDR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct fsl_sai *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case FSL_SAI_TDR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case FSL_SAI_TDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) case FSL_SAI_TDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case FSL_SAI_TDR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case FSL_SAI_TDR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case FSL_SAI_TDR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) case FSL_SAI_TDR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case FSL_SAI_TDR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case FSL_SAI_TMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case FSL_SAI_RMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case FSL_SAI_MCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case FSL_SAI_MDIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case FSL_SAI_TTCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case FSL_SAI_RTCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static struct regmap_config fsl_sai_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .max_register = FSL_SAI_RMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .reg_defaults = fsl_sai_reg_defaults_ofs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .readable_reg = fsl_sai_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .volatile_reg = fsl_sai_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .writeable_reg = fsl_sai_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int fsl_sai_check_version(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct fsl_sai *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) unsigned char ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_dbg(dev, "VERID: 0x%016X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) FSL_SAI_VERID_MAJOR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) FSL_SAI_VERID_MINOR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_dbg(dev, "PARAM: 0x%016X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Max slots per frame, power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) sai->param.slot_num = 1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Words per fifo, power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) sai->param.fifo_depth = 1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Number of datalines implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static int fsl_sai_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct fsl_sai *sai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) char tmp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int irq, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (!sai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) sai->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) sai->soc_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (sai->soc_data->reg_offset == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) fsl_sai_regmap_config.num_reg_defaults =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) "bus", base, &fsl_sai_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Compatible with old DTB cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "sai", base, &fsl_sai_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (IS_ERR(sai->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return PTR_ERR(sai->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* No error out for old DTB cases but only mark the clock NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (IS_ERR(sai->bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PTR_ERR(sai->bus_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) sai->bus_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) sai->mclk_clk[0] = sai->bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) sprintf(tmp, "mclk%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (IS_ERR(sai->mclk_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) i + 1, PTR_ERR(sai->mclk_clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) sai->mclk_clk[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) np->name, sai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) sizeof(fsl_sai_dai_template));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Sync Tx with Rx as default by following old DT binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) sai->synchronous[RX] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) sai->synchronous[TX] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) sai->cpu_dai_drv.symmetric_rates = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) sai->cpu_dai_drv.symmetric_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) sai->cpu_dai_drv.symmetric_samplebits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) of_find_property(np, "fsl,sai-asynchronous", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* error out if both synchronous and asynchronous are present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Sync Rx with Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) sai->synchronous[RX] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) sai->synchronous[TX] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Discard all settings for asynchronous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) sai->synchronous[RX] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) sai->synchronous[TX] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) sai->cpu_dai_drv.symmetric_rates = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) sai->cpu_dai_drv.symmetric_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) sai->cpu_dai_drv.symmetric_samplebits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) of_device_is_compatible(np, "fsl,imx6ul-sai")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (IS_ERR(gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_err(&pdev->dev, "cannot find iomuxc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return PTR_ERR(gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) index = of_alias_get_id(np, "sai");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) MCLK_DIR(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) platform_set_drvdata(pdev, sai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Get sai version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = fsl_sai_check_version(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Select MCLK direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) sai->verid.major >= 3 && sai->verid.minor >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) regcache_cache_only(sai->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) &sai->cpu_dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (sai->soc_data->use_imx_pcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int fsl_sai_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .use_imx_pcm = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .use_edma = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .fifo_depth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .use_imx_pcm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .use_edma = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .fifo_depth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .use_imx_pcm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .use_edma = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .fifo_depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .reg_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .use_imx_pcm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .use_edma = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .fifo_depth = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .reg_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .use_imx_pcm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .use_edma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .fifo_depth = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const struct of_device_id fsl_sai_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) MODULE_DEVICE_TABLE(of, fsl_sai_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int fsl_sai_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct fsl_sai *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) clk_disable_unprepare(sai->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) regcache_cache_only(sai->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int fsl_sai_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct fsl_sai *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) unsigned int ofs = sai->soc_data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ret = clk_prepare_enable(sai->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_err(dev, "failed to enable bus clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) goto disable_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) goto disable_tx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) regcache_cache_only(sai->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) regcache_mark_dirty(sai->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = regcache_sync(sai->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) goto disable_rx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) disable_rx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) disable_tx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) disable_bus_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) clk_disable_unprepare(sai->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static const struct dev_pm_ops fsl_sai_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) fsl_sai_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static struct platform_driver fsl_sai_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .probe = fsl_sai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .remove = fsl_sai_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .name = "fsl-sai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .pm = &fsl_sai_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .of_match_table = fsl_sai_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) module_platform_driver(fsl_sai_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MODULE_DESCRIPTION("Freescale Soc SAI Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) MODULE_ALIAS("platform:fsl-sai");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags