Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // ALSA SoC IMX MQS driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_MQS_CTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MQS_EN_MASK			(0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MQS_EN_SHIFT			(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MQS_SW_RST_MASK			(0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MQS_SW_RST_SHIFT		(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MQS_OVERSAMPLE_MASK		(0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MQS_OVERSAMPLE_SHIFT		(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MQS_CLK_DIV_MASK		(0xFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MQS_CLK_DIV_SHIFT		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* codec private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct fsl_mqs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct clk *ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int reg_iomuxc_gpr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int reg_mqs_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	bool use_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define FSL_MQS_RATES	(SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define FSL_MQS_FORMATS	SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			     struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			     struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int div, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int lrclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	mclk_rate = clk_get_rate(mqs_priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	lrclk = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * if repeat_rate is 8, mqs can achieve better quality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * oversample rate is fix to 32 currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	div = mclk_rate / (32 * lrclk * 2 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	res = mclk_rate % (32 * lrclk * 2 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (res == 0 && div > 0 && div <= 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (mqs_priv->use_gpr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					   IMX6SX_GPR2_MQS_CLK_DIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 					   (div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					   IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					   MQS_CLK_DIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					   (div - 1) << MQS_CLK_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 					   MQS_OVERSAMPLE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		dev_err(component->dev, "can't get proper divider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* Only LEFT_J & SLAVE mode is supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int fsl_mqs_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			   struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (mqs_priv->use_gpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				   IMX6SX_GPR2_MQS_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				   1 << IMX6SX_GPR2_MQS_EN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				   MQS_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				   1 << MQS_EN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			     struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (mqs_priv->use_gpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				   IMX6SX_GPR2_MQS_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				   MQS_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.idle_bias_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.non_legacy_dai_naming	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.startup = fsl_mqs_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.shutdown = fsl_mqs_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.hw_params = fsl_mqs_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.set_fmt = fsl_mqs_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct snd_soc_dai_driver fsl_mqs_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.name		= "fsl-mqs-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.playback	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.stream_name	= "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.rates		= FSL_MQS_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.formats	= FSL_MQS_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.ops = &fsl_mqs_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct regmap_config fsl_mqs_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.max_register = REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int fsl_mqs_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct device_node *gpr_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct fsl_mqs *mqs_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!mqs_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* On i.MX6sx the MQS control register is in GPR domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * But in i.MX8QM/i.MX8QXP the control register is moved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * to its own domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (of_device_is_compatible(np, "fsl,imx8qm-mqs"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		mqs_priv->use_gpr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		mqs_priv->use_gpr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (mqs_priv->use_gpr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		gpr_np = of_parse_phandle(np, "gpr", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (!gpr_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (IS_ERR(mqs_priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			dev_err(&pdev->dev, "failed to get gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			ret = PTR_ERR(mqs_priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			goto err_free_gpr_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 							     "core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 							     regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 							     &fsl_mqs_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (IS_ERR(mqs_priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			dev_err(&pdev->dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				PTR_ERR(mqs_priv->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			return PTR_ERR(mqs_priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (IS_ERR(mqs_priv->ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			dev_err(&pdev->dev, "failed to get the clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				PTR_ERR(mqs_priv->ipg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			return PTR_ERR(mqs_priv->ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (IS_ERR(mqs_priv->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		dev_err(&pdev->dev, "failed to get the clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			PTR_ERR(mqs_priv->mclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ret = PTR_ERR(mqs_priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		goto err_free_gpr_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dev_set_drvdata(&pdev->dev, mqs_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			&fsl_mqs_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		goto err_free_gpr_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err_free_gpr_np:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	of_node_put(gpr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int fsl_mqs_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int fsl_mqs_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ret = clk_prepare_enable(mqs_priv->ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dev_err(dev, "failed to enable ipg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ret = clk_prepare_enable(mqs_priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		dev_err(dev, "failed to enable mclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		clk_disable_unprepare(mqs_priv->ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (mqs_priv->use_gpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		regmap_write(mqs_priv->regmap, IOMUXC_GPR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			     mqs_priv->reg_iomuxc_gpr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		regmap_write(mqs_priv->regmap, REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			     mqs_priv->reg_mqs_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int fsl_mqs_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (mqs_priv->use_gpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		regmap_read(mqs_priv->regmap, IOMUXC_GPR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			    &mqs_priv->reg_iomuxc_gpr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		regmap_read(mqs_priv->regmap, REG_MQS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			    &mqs_priv->reg_mqs_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	clk_disable_unprepare(mqs_priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	clk_disable_unprepare(mqs_priv->ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct dev_pm_ops fsl_mqs_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			   fsl_mqs_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			   NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 				pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct of_device_id fsl_mqs_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ .compatible = "fsl,imx8qm-mqs", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{ .compatible = "fsl,imx6sx-mqs", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct platform_driver fsl_mqs_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.probe		= fsl_mqs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.remove		= fsl_mqs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.name	= "fsl-mqs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.of_match_table = fsl_mqs_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.pm = &fsl_mqs_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) module_platform_driver(fsl_mqs_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DESCRIPTION("MQS codec driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_ALIAS("platform:fsl-mqs");