Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PDM Microphone Interface for the NXP i.MX SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _FSL_MICFIL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _FSL_MICFIL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* MICFIL Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define REG_MICFIL_CTRL1		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define REG_MICFIL_CTRL2		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define REG_MICFIL_STAT			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define REG_MICFIL_FIFO_CTRL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define REG_MICFIL_FIFO_STAT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define REG_MICFIL_DATACH0		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define REG_MICFIL_DATACH1		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_MICFIL_DATACH2		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_MICFIL_DATACH3		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_MICFIL_DATACH4		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_MICFIL_DATACH5		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_MICFIL_DATACH6		0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_MICFIL_DATACH7		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_MICFIL_DC_CTRL		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_MICFIL_OUT_CTRL		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_MICFIL_OUT_STAT		0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_MICFIL_VAD0_CTRL1		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_MICFIL_VAD0_CTRL2		0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_MICFIL_VAD0_STAT		0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_MICFIL_VAD0_SCONFIG		0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_MICFIL_VAD0_NCONFIG		0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_MICFIL_VAD0_NDATA		0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_MICFIL_VAD0_ZCD		0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MICFIL_CTRL1_MDIS_SHIFT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MICFIL_CTRL1_MDIS_MASK		BIT(MICFIL_CTRL1_MDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MICFIL_CTRL1_MDIS		BIT(MICFIL_CTRL1_MDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MICFIL_CTRL1_DOZEN_SHIFT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MICFIL_CTRL1_DOZEN_MASK		BIT(MICFIL_CTRL1_DOZEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MICFIL_CTRL1_DOZEN		BIT(MICFIL_CTRL1_DOZEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MICFIL_CTRL1_PDMIEN_SHIFT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MICFIL_CTRL1_PDMIEN_MASK	BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MICFIL_CTRL1_PDMIEN		BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MICFIL_CTRL1_DBG_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MICFIL_CTRL1_DBG_MASK		BIT(MICFIL_CTRL1_DBG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MICFIL_CTRL1_DBG		BIT(MICFIL_CTRL1_DBG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MICFIL_CTRL1_SRES_SHIFT		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MICFIL_CTRL1_SRES_MASK		BIT(MICFIL_CTRL1_SRES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MICFIL_CTRL1_SRES		BIT(MICFIL_CTRL1_SRES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MICFIL_CTRL1_DBGE_SHIFT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MICFIL_CTRL1_DBGE_MASK		BIT(MICFIL_CTRL1_DBGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MICFIL_CTRL1_DBGE		BIT(MICFIL_CTRL1_DBGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MICFIL_CTRL1_DISEL_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MICFIL_CTRL1_DISEL_WIDTH	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MICFIL_CTRL1_DISEL_MASK		((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					 << MICFIL_CTRL1_DISEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MICFIL_CTRL1_DISEL(v)		(((v) << MICFIL_CTRL1_DISEL_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 					 & MICFIL_CTRL1_DISEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MICFIL_CTRL1_ERREN_SHIFT	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MICFIL_CTRL1_ERREN_MASK		BIT(MICFIL_CTRL1_ERREN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MICFIL_CTRL1_ERREN		BIT(MICFIL_CTRL1_ERREN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MICFIL_CTRL1_CHEN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MICFIL_CTRL1_CHEN_WIDTH		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MICFIL_CTRL1_CHEN_MASK(x)	(BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MICFIL_CTRL1_CHEN(x)		(MICFIL_CTRL1_CHEN_MASK(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MICFIL_CTRL2_QSEL_SHIFT		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MICFIL_CTRL2_QSEL_WIDTH		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MICFIL_CTRL2_QSEL_MASK		((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					 << MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MICFIL_HIGH_QUALITY		BIT(MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MICFIL_MEDIUM_QUALITY		(0 << MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MICFIL_LOW_QUALITY		(7 << MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MICFIL_VLOW0_QUALITY		(6 << MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MICFIL_VLOW1_QUALITY		(5 << MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MICFIL_VLOW2_QUALITY		(4 << MICFIL_CTRL2_QSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MICFIL_CTRL2_CICOSR_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MICFIL_CTRL2_CICOSR_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MICFIL_CTRL2_CICOSR_MASK	((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					 << MICFIL_CTRL2_CICOSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MICFIL_CTRL2_CICOSR(v)		(((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					 & MICFIL_CTRL2_CICOSR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MICFIL_CTRL2_CLKDIV_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MICFIL_CTRL2_CLKDIV_WIDTH	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MICFIL_CTRL2_CLKDIV_MASK	((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					 << MICFIL_CTRL2_CLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MICFIL_CTRL2_CLKDIV(v)		(((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 					 & MICFIL_CTRL2_CLKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MICFIL_STAT_BSY_FIL_SHIFT	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MICFIL_STAT_BSY_FIL_MASK	BIT(MICFIL_STAT_BSY_FIL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MICFIL_STAT_BSY_FIL		BIT(MICFIL_STAT_BSY_FIL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MICFIL_STAT_FIR_RDY_SHIFT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MICFIL_STAT_FIR_RDY_MASK	BIT(MICFIL_STAT_FIR_RDY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MICFIL_STAT_FIR_RDY		BIT(MICFIL_STAT_FIR_RDY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MICFIL_STAT_LOWFREQF_SHIFT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MICFIL_STAT_LOWFREQF_MASK	BIT(MICFIL_STAT_LOWFREQF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MICFIL_STAT_LOWFREQF		BIT(MICFIL_STAT_LOWFREQF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MICFIL_STAT_CHXF_SHIFT(v)	(v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MICFIL_STAT_CHXF_MASK(v)	BIT(MICFIL_STAT_CHXF_SHIFT(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MICFIL_STAT_CHXF(v)		BIT(MICFIL_STAT_CHXF_SHIFT(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MICFIL_FIFO_CTRL_FIFOWMK_MASK	((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 					 << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MICFIL_FIFO_CTRL_FIFOWMK(v)	(((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					 & MICFIL_FIFO_CTRL_FIFOWMK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)	(v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v)	BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v)	((v) + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v)	BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MICFIL_VAD0_CTRL1_CHSEL_WIDTH	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MICFIL_VAD0_CTRL1_CHSEL_MASK	((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					 << MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MICFIL_VAD0_CTRL1_CHSEL(v)	(((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 					 & MICFIL_VAD0_CTRL1_CHSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MICFIL_VAD0_CTRL1_CICOSR_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MICFIL_VAD0_CTRL1_CICOSR_MASK	((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					 << MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MICFIL_VAD0_CTRL1_CICOSR(v)	(((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					 & MICFIL_VAD0_CTRL1_CICOSR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MICFIL_VAD0_CTRL1_INITT_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MICFIL_VAD0_CTRL1_INITT_WIDTH	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MICFIL_VAD0_CTRL1_INITT_MASK	((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					 << MICFIL_VAD0_CTRL1_INITT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MICFIL_VAD0_CTRL1_INITT(v)	(((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 					 & MICFIL_VAD0_CTRL1_INITT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MICFIL_VAD0_CTRL1_ST10_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MICFIL_VAD0_CTRL1_ST10_MASK	BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MICFIL_VAD0_CTRL1_ST10		BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MICFIL_VAD0_CTRL1_ERIE_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MICFIL_VAD0_CTRL1_ERIE_MASK	BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MICFIL_VAD0_CTRL1_ERIE		BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MICFIL_VAD0_CTRL1_IE_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MICFIL_VAD0_CTRL1_IE_MASK	BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MICFIL_VAD0_CTRL1_IE		BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MICFIL_VAD0_CTRL1_RST_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MICFIL_VAD0_CTRL1_RST_MASK	BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MICFIL_VAD0_CTRL1_RST		BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MICFIL_VAD0_CTRL1_EN_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MICFIL_VAD0_CTRL1_EN_MASK	BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MICFIL_VAD0_CTRL1_EN		BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MICFIL_VAD0_CTRL2_FRENDIS_MASK	BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MICFIL_VAD0_CTRL2_FRENDIS	BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MICFIL_VAD0_CTRL2_PREFEN_SHIFT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MICFIL_VAD0_CTRL2_PREFEN_MASK	BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MICFIL_VAD0_CTRL2_PREFEN	BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MICFIL_VAD0_CTRL2_FOUTDIS_MASK	BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MICFIL_VAD0_CTRL2_FOUTDIS	BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MICFIL_VAD0_CTRL2_FRAMET_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MICFIL_VAD0_CTRL2_FRAMET_WIDTH	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MICFIL_VAD0_CTRL2_FRAMET_MASK	((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					 << MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MICFIL_VAD0_CTRL2_FRAMET(v)	(((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					 & MICFIL_VAD0_CTRL2_FRAMET_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MICFIL_VAD0_CTRL2_INPGAIN_MASK	((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 					 << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MICFIL_VAD0_CTRL2_INPGAIN(v)	(((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					& MICFIL_VAD0_CTRL2_INPGAIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MICFIL_VAD0_CTRL2_HPF_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MICFIL_VAD0_CTRL2_HPF_WIDTH	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MICFIL_VAD0_CTRL2_HPF_MASK	((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					 << MICFIL_VAD0_CTRL2_HPF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MICFIL_VAD0_CTRL2_HPF(v)	(((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					 & MICFIL_VAD0_CTRL2_HPF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MICFIL_VAD0_SCONFIG_SFILEN_MASK		BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MICFIL_VAD0_SCONFIG_SFILEN		BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MICFIL_VAD0_SCONFIG_SMAXEN_MASK		BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MICFIL_VAD0_SCONFIG_SMAXEN		BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MICFIL_VAD0_SCONFIG_SGAIN_MASK		((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 						<< MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MICFIL_VAD0_SCONFIG_SGAIN(v)		(((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 						 & MICFIL_VAD0_SCONFIG_SGAIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MICFIL_VAD0_NCONFIG_NFILAUT_MASK	BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MICFIL_VAD0_NCONFIG_NFILAUT		BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MICFIL_VAD0_NCONFIG_NMINEN_MASK		BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MICFIL_VAD0_NCONFIG_NMINEN		BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MICFIL_VAD0_NCONFIG_NDECEN_MASK		BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MICFIL_VAD0_NCONFIG_NDECEN		BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MICFIL_VAD0_NCONFIG_NOREN_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MICFIL_VAD0_NCONFIG_NOREN		BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MICFIL_VAD0_NCONFIG_NFILADJ_MASK	((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 						 << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MICFIL_VAD0_NCONFIG_NFILADJ(v)		(((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 						 & MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MICFIL_VAD0_NCONFIG_NGAIN_MASK		((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 						 << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MICFIL_VAD0_NCONFIG_NGAIN(v)		(((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 						 & MICFIL_VAD0_NCONFIG_NGAIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MICFIL_VAD0_ZCD_ZCDTH_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MICFIL_VAD0_ZCD_ZCDTH_WIDTH	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MICFIL_VAD0_ZCD_ZCDTH_MASK	((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					 << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MICFIL_VAD0_ZCD_ZCDTH(v)	(((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 					 & MICFIL_VAD0_ZCD_ZCDTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MICFIL_VAD0_ZCD_ZCDADJ_MASK	((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					 << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MICFIL_VAD0_ZCD_ZCDADJ(v)	(((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					 & MICFIL_VAD0_ZCD_ZCDADJ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MICFIL_VAD0_ZCD_ZCDAND_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MICFIL_VAD0_ZCD_ZCDAND_MASK	BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MICFIL_VAD0_ZCD_ZCDAND		BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MICFIL_VAD0_ZCD_ZCDAUT_MASK	BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MICFIL_VAD0_ZCD_ZCDAUT		BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MICFIL_VAD0_ZCD_ZCDEN_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MICFIL_VAD0_ZCD_ZCDEN_MASK	BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MICFIL_VAD0_ZCD_ZCDEN		BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MICFIL_VAD0_STAT_INITF_SHIFT	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MICFIL_VAD0_STAT_INITF_MASK	BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MICFIL_VAD0_STAT_INITF		BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MICFIL_VAD0_STAT_INSATF_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MICFIL_VAD0_STAT_INSATF_MASK	BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MICFIL_VAD0_STAT_INSATF		BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MICFIL_VAD0_STAT_EF_SHIFT	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MICFIL_VAD0_STAT_EF_MASK	BIT(MICFIL_VAD0_STAT_EF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MICFIL_VAD0_STAT_EF		BIT(MICFIL_VAD0_STAT_EF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MICFIL_VAD0_STAT_IF_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MICFIL_VAD0_STAT_IF_MASK	BIT(MICFIL_VAD0_STAT_IF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MICFIL_VAD0_STAT_IF		BIT(MICFIL_VAD0_STAT_IF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* MICFIL Output Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MICFIL_OUTGAIN_CHX_SHIFT(v)	(4 * (v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MICFIL_DMA_IRQ_DISABLED(v)	((v) & MICFIL_CTRL1_DISEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MICFIL_DMA_ENABLED(v)		((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 					 == ((v) & MICFIL_CTRL1_DISEL_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MICFIL_IRQ_ENABLED(v)		((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					 == ((v) & MICFIL_CTRL1_DISEL_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MICFIL_OUTPUT_CHANNELS		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MICFIL_FIFO_NUM			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define FIFO_PTRWID			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FIFO_LEN			BIT(FIFO_PTRWID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MICFIL_IRQ_LINES		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MICFIL_MAX_RETRY		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MICFIL_SLEEP_MIN		90000 /* in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MICFIL_SLEEP_MAX		100000 /* in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MICFIL_DMA_MAXBURST_RX		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MICFIL_CTRL2_OSR_DEFAULT	(0 << MICFIL_CTRL2_CICOSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif /* _FSL_MICFIL_H */