^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "fsl_micfil.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct fsl_micfil {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct fsl_micfil_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct snd_dmaengine_dai_dma_data dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int dataline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int irq[MICFIL_IRQ_LINES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int mclk_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int quality; /*QUALITY 2-0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int channel_gain[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct fsl_micfil_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int fifos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int dataline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) bool imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .imx = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .fifos = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .fifo_depth = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .dataline = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct of_device_id fsl_micfil_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Table 5. Quality Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Medium 0 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * High 0 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Very Low 2 1 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Very Low 1 1 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Very Low 0 1 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Low 1 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const char * const micfil_quality_select_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "Medium", "High",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "N/A", "N/A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "VLow2", "VLow1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "VLow0", "Low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct soc_enum fsl_micfil_quality_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MICFIL_CTRL2_QSEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ARRAY_SIZE(micfil_quality_select_texts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) micfil_quality_select_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SOC_ENUM_EXT("MICFIL Quality Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fsl_micfil_quality_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) snd_soc_get_enum_double, snd_soc_put_enum_double),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline int get_pdm_clk(struct fsl_micfil *micfil,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 ctrl2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int qsel, osr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) >> MICFIL_CTRL2_CICOSR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) switch (qsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case MICFIL_HIGH_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case MICFIL_MEDIUM_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case MICFIL_VLOW0_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bclk = rate * 4 * osr * 1; /* kfactor = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case MICFIL_LOW_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case MICFIL_VLOW1_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bclk = rate * 2 * osr * 2; /* kfactor = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case MICFIL_VLOW2_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bclk = rate * osr * 4; /* kfactor = 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(&micfil->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "Please make sure you select a valid quality.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bclk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline int get_clk_div(struct fsl_micfil *micfil,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 ctrl2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) long mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mclk_rate = clk_get_rate(micfil->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* The SRES is a self-negated bit which provides the CPU with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * capability to initialize the PDM Interface module through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * slave-bus interface. This bit always reads as zero, and this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * bit is only effective when MDIS is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int fsl_micfil_reset(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct fsl_micfil *micfil = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_update_bits(micfil->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MICFIL_CTRL1_MDIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(dev, "failed to clear MDIS bit %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = regmap_update_bits(micfil->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MICFIL_CTRL1_SRES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MICFIL_CTRL1_SRES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(dev, "failed to reset MICFIL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct device *dev = &micfil->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_disable_unprepare(micfil->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = clk_set_rate(micfil->mclk, freq * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_warn(dev, "failed to set rate (%u): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) freq * 1024, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk_prepare_enable(micfil->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int fsl_micfil_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!micfil) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(dai->dev, "micfil dai priv_data not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device *dev = &micfil->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = fsl_micfil_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(dev, "failed to soft reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* DMA Interrupt Selection - DISEL bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * 00 - DMA and IRQ disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * 01 - DMA req enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * 10 - IRQ enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * 11 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MICFIL_CTRL1_DISEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (1 << MICFIL_CTRL1_DISEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dev, "failed to update DISEL bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Enable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MICFIL_CTRL1_PDMIEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MICFIL_CTRL1_PDMIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(dev, "failed to enable the module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Disable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MICFIL_CTRL1_PDMIEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "failed to enable the module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MICFIL_CTRL1_DISEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (0 << MICFIL_CTRL1_DISEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_err(dev, "failed to update DISEL bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int fsl_set_clock_params(struct device *dev, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct fsl_micfil *micfil = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = fsl_micfil_set_mclk_rate(micfil, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_get_rate(micfil->mclk), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* set CICOSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MICFIL_CTRL2_CICOSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MICFIL_CTRL2_OSR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) REG_MICFIL_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* set CLK_DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk_div = get_clk_div(micfil, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (clk_div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MICFIL_CTRL2_CLKDIV_MASK, clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) REG_MICFIL_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device *dev = &micfil->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* 1. Disable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MICFIL_CTRL1_PDMIEN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(dev, "failed to disable the module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* enable channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0xFF, ((1 << channels) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) REG_MICFIL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = fsl_set_clock_params(dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct device *dev = &micfil->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = fsl_micfil_set_mclk_rate(micfil, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk_get_rate(micfil->mclk), freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct snd_soc_dai_ops fsl_micfil_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .startup = fsl_micfil_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .trigger = fsl_micfil_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .hw_params = fsl_micfil_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .set_sysclk = fsl_micfil_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct device *dev = cpu_dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* set qsel to medium */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) REG_MICFIL_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* set default gain to max_gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) micfil->channel_gain[i] = 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) snd_soc_dai_init_dma_data(cpu_dai, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &micfil->dma_params_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* FIFO Watermark Control - FIFOWMK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MICFIL_FIFO_CTRL_FIFOWMK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(dev, "failed to set FIFOWMK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) snd_soc_dai_set_drvdata(cpu_dai, micfil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static struct snd_soc_dai_driver fsl_micfil_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .probe = fsl_micfil_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .stream_name = "CPU-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .rates = FSL_MICFIL_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .formats = FSL_MICFIL_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ops = &fsl_micfil_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct snd_soc_component_driver fsl_micfil_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "fsl-micfil-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .controls = fsl_micfil_snd_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* REGMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct reg_default fsl_micfil_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {REG_MICFIL_CTRL1, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {REG_MICFIL_CTRL2, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {REG_MICFIL_STAT, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {REG_MICFIL_FIFO_CTRL, 0x00000007},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {REG_MICFIL_FIFO_STAT, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {REG_MICFIL_DATACH0, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {REG_MICFIL_DATACH1, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {REG_MICFIL_DATACH2, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {REG_MICFIL_DATACH3, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {REG_MICFIL_DATACH4, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {REG_MICFIL_DATACH5, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {REG_MICFIL_DATACH6, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {REG_MICFIL_DATACH7, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {REG_MICFIL_DC_CTRL, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {REG_MICFIL_OUT_CTRL, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {REG_MICFIL_OUT_STAT, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {REG_MICFIL_VAD0_CTRL1, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {REG_MICFIL_VAD0_STAT, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {REG_MICFIL_VAD0_NDATA, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {REG_MICFIL_VAD0_ZCD, 0x00000004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case REG_MICFIL_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case REG_MICFIL_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case REG_MICFIL_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case REG_MICFIL_FIFO_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case REG_MICFIL_FIFO_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case REG_MICFIL_DATACH0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case REG_MICFIL_DATACH1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case REG_MICFIL_DATACH2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case REG_MICFIL_DATACH3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case REG_MICFIL_DATACH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case REG_MICFIL_DATACH5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case REG_MICFIL_DATACH6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case REG_MICFIL_DATACH7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case REG_MICFIL_DC_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case REG_MICFIL_OUT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case REG_MICFIL_OUT_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case REG_MICFIL_VAD0_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case REG_MICFIL_VAD0_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case REG_MICFIL_VAD0_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case REG_MICFIL_VAD0_SCONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case REG_MICFIL_VAD0_NCONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case REG_MICFIL_VAD0_NDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case REG_MICFIL_VAD0_ZCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case REG_MICFIL_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case REG_MICFIL_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case REG_MICFIL_STAT: /* Write 1 to Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case REG_MICFIL_FIFO_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case REG_MICFIL_DC_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case REG_MICFIL_OUT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case REG_MICFIL_VAD0_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case REG_MICFIL_VAD0_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case REG_MICFIL_VAD0_SCONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case REG_MICFIL_VAD0_NCONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case REG_MICFIL_VAD0_ZCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case REG_MICFIL_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case REG_MICFIL_DATACH0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case REG_MICFIL_DATACH1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case REG_MICFIL_DATACH2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case REG_MICFIL_DATACH3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case REG_MICFIL_DATACH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case REG_MICFIL_DATACH5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case REG_MICFIL_DATACH6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case REG_MICFIL_DATACH7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case REG_MICFIL_VAD0_STAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case REG_MICFIL_VAD0_NDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct regmap_config fsl_micfil_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .max_register = REG_MICFIL_VAD0_ZCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .reg_defaults = fsl_micfil_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .readable_reg = fsl_micfil_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .volatile_reg = fsl_micfil_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .writeable_reg = fsl_micfil_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* END OF REGMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static irqreturn_t micfil_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct platform_device *pdev = micfil->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 stat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 fifo_stat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 ctrl1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) bool dma_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Channel 0-7 Output Data Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "Data available in Data Channel %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* if DMA is not enabled, field must be written with 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!dma_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) regmap_write_bits(micfil->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) REG_MICFIL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MICFIL_STAT_CHXF_MASK(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) for (i = 0; i < MICFIL_FIFO_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) "FIFO Overflow Exception flag for channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "FIFO Underflow Exception flag for channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static irqreturn_t micfil_err_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct platform_device *pdev = micfil->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 stat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MICFIL_STAT_LOWFREQF_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int fsl_micfil_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct fsl_micfil *micfil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned long irqflag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!micfil)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) micfil->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) of_id = of_match_device(fsl_micfil_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!of_id || !of_id->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) micfil->soc = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* ipg_clk is used to control the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * ipg_clk_app is used to operate the filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (IS_ERR(micfil->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(&pdev->dev, "failed to get core clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PTR_ERR(micfil->mclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return PTR_ERR(micfil->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* init regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "ipg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &fsl_micfil_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (IS_ERR(micfil->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PTR_ERR(micfil->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return PTR_ERR(micfil->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* dataline mask for RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = of_property_read_u32_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "fsl,dataline",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &micfil->dataline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) micfil->dataline = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (micfil->dataline & ~micfil->soc->dataline) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) micfil->soc->dataline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* get IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) for (i = 0; i < MICFIL_IRQ_LINES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) micfil->irq[i] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (micfil->irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return micfil->irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (of_property_read_bool(np, "fsl,shared-interrupt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) irqflag = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Digital Microphone interface interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = devm_request_irq(&pdev->dev, micfil->irq[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) micfil_isr, irqflag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) micfil->name, micfil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) micfil->irq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Digital Microphone interface error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = devm_request_irq(&pdev->dev, micfil->irq[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) micfil_err_isr, irqflag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) micfil->name, micfil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) micfil->irq[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) micfil->dma_params_rx.chan_name = "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) platform_set_drvdata(pdev, micfil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) &fsl_micfil_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_err(&pdev->dev, "failed to register component %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) fsl_micfil_component.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(&pdev->dev, "failed to pcm register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct fsl_micfil *micfil = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) regcache_cache_only(micfil->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) clk_disable_unprepare(micfil->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct fsl_micfil *micfil = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = clk_prepare_enable(micfil->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) regcache_cache_only(micfil->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) regcache_mark_dirty(micfil->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) regcache_sync(micfil->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int __maybe_unused fsl_micfil_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int __maybe_unused fsl_micfil_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const struct dev_pm_ops fsl_micfil_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fsl_micfil_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) fsl_micfil_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static struct platform_driver fsl_micfil_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .probe = fsl_micfil_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .name = "fsl-micfil-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .pm = &fsl_micfil_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .of_match_table = fsl_micfil_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) module_platform_driver(fsl_micfil_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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