Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * fsl_esai.h - ALSA ESAI interface for the Freescale i.MX SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _FSL_ESAI_DAI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _FSL_ESAI_DAI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* ESAI Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define REG_ESAI_ETDR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define REG_ESAI_ERDR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define REG_ESAI_ECR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define REG_ESAI_ESR		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_ESAI_TFCR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_ESAI_TFSR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_ESAI_RFCR		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_ESAI_RFSR		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_ESAI_xFCR(tx)	(tx ? REG_ESAI_TFCR : REG_ESAI_RFCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_ESAI_xFSR(tx)	(tx ? REG_ESAI_TFSR : REG_ESAI_RFSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_ESAI_TX0		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_ESAI_TX1		0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_ESAI_TX2		0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_ESAI_TX3		0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_ESAI_TX4		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_ESAI_TX5		0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_ESAI_TSR		0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_ESAI_RX0		0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_ESAI_RX1		0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_ESAI_RX2		0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_ESAI_RX3		0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_ESAI_SAISR		0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_ESAI_SAICR		0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_ESAI_TCR		0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_ESAI_TCCR		0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_ESAI_RCR		0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_ESAI_RCCR		0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_ESAI_xCR(tx)	(tx ? REG_ESAI_TCR : REG_ESAI_RCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REG_ESAI_xCCR(tx)	(tx ? REG_ESAI_TCCR : REG_ESAI_RCCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define REG_ESAI_TSMA		0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REG_ESAI_TSMB		0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_ESAI_RSMA		0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define REG_ESAI_RSMB		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define REG_ESAI_xSMA(tx)	(tx ? REG_ESAI_TSMA : REG_ESAI_RSMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REG_ESAI_xSMB(tx)	(tx ? REG_ESAI_TSMB : REG_ESAI_RSMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG_ESAI_PRRC		0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define REG_ESAI_PCRC		0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* ESAI Control Register -- REG_ESAI_ECR 0x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ESAI_ECR_ETI_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ESAI_ECR_ETI_MASK	(1 << ESAI_ECR_ETI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ESAI_ECR_ETI		(1 << ESAI_ECR_ETI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ESAI_ECR_ETO_SHIFT	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ESAI_ECR_ETO_MASK	(1 << ESAI_ECR_ETO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ESAI_ECR_ETO		(1 << ESAI_ECR_ETO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ESAI_ECR_ERI_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ESAI_ECR_ERI_MASK	(1 << ESAI_ECR_ERI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ESAI_ECR_ERI		(1 << ESAI_ECR_ERI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ESAI_ECR_ERO_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ESAI_ECR_ERO_MASK	(1 << ESAI_ECR_ERO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ESAI_ECR_ERO		(1 << ESAI_ECR_ERO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ESAI_ECR_ERST_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ESAI_ECR_ERST_MASK	(1 << ESAI_ECR_ERST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define ESAI_ECR_ERST		(1 << ESAI_ECR_ERST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ESAI_ECR_ESAIEN_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define ESAI_ECR_ESAIEN_MASK	(1 << ESAI_ECR_ESAIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ESAI_ECR_ESAIEN		(1 << ESAI_ECR_ESAIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* ESAI Status Register -- REG_ESAI_ESR 0xC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define ESAI_ESR_TINIT_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define ESAI_ESR_TINIT_MASK	(1 << ESAI_ESR_TINIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ESAI_ESR_TINIT		(1 << ESAI_ESR_TINIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ESAI_ESR_RFF_SHIFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define ESAI_ESR_RFF_MASK	(1 << ESAI_ESR_RFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ESAI_ESR_RFF		(1 << ESAI_ESR_RFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ESAI_ESR_TFE_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define ESAI_ESR_TFE_MASK	(1 << ESAI_ESR_TFE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ESAI_ESR_TFE		(1 << ESAI_ESR_TFE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define ESAI_ESR_TLS_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define ESAI_ESR_TLS_MASK	(1 << ESAI_ESR_TLS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ESAI_ESR_TLS		(1 << ESAI_ESR_TLS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ESAI_ESR_TDE_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ESAI_ESR_TDE_MASK	(1 << ESAI_ESR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ESAI_ESR_TDE		(1 << ESAI_ESR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define ESAI_ESR_TED_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ESAI_ESR_TED_MASK	(1 << ESAI_ESR_TED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ESAI_ESR_TED		(1 << ESAI_ESR_TED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ESAI_ESR_TD_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ESAI_ESR_TD_MASK	(1 << ESAI_ESR_TD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ESAI_ESR_TD		(1 << ESAI_ESR_TD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ESAI_ESR_RLS_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ESAI_ESR_RLS_MASK	(1 << ESAI_ESR_RLS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ESAI_ESR_RLS		(1 << ESAI_ESR_RLS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ESAI_ESR_RDE_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ESAI_ESR_RDE_MASK	(1 << ESAI_ESR_RDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ESAI_ESR_RDE		(1 << ESAI_ESR_RDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ESAI_ESR_RED_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ESAI_ESR_RED_MASK	(1 << ESAI_ESR_RED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ESAI_ESR_RED		(1 << ESAI_ESR_RED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ESAI_ESR_RD_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ESAI_ESR_RD_MASK	(1 << ESAI_ESR_RD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ESAI_ESR_RD		(1 << ESAI_ESR_RD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * Transmit FIFO Configuration Register -- REG_ESAI_TFCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * Receive FIFO Configuration Register -- REG_ESAI_RFCR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ESAI_xFCR_TIEN_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ESAI_xFCR_TIEN_MASK	(1 << ESAI_xFCR_TIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ESAI_xFCR_TIEN		(1 << ESAI_xFCR_TIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ESAI_xFCR_REXT_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ESAI_xFCR_REXT_MASK	(1 << ESAI_xFCR_REXT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ESAI_xFCR_REXT		(1 << ESAI_xFCR_REXT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ESAI_xFCR_xWA_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ESAI_xFCR_xWA_WIDTH	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ESAI_xFCR_xWA_MASK	(((1 << ESAI_xFCR_xWA_WIDTH) - 1) << ESAI_xFCR_xWA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ESAI_xFCR_xWA(v)	(((8 - ((v) >> 2)) << ESAI_xFCR_xWA_SHIFT) & ESAI_xFCR_xWA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ESAI_xFCR_xFWM_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ESAI_xFCR_xFWM_WIDTH	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ESAI_xFCR_xFWM_MASK	(((1 << ESAI_xFCR_xFWM_WIDTH) - 1) << ESAI_xFCR_xFWM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ESAI_xFCR_xFWM(v)	((((v) - 1) << ESAI_xFCR_xFWM_SHIFT) & ESAI_xFCR_xFWM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ESAI_xFCR_xE_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ESAI_xFCR_TE_WIDTH	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ESAI_xFCR_RE_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ESAI_xFCR_TE_MASK	(((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ESAI_xFCR_RE_MASK	(((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ESAI_xFCR_TE(x) 	((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - x)) & ESAI_xFCR_TE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ESAI_xFCR_RE(x) 	((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - x)) & ESAI_xFCR_RE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ESAI_xFCR_xFR_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ESAI_xFCR_xFR_MASK	(1 << ESAI_xFCR_xFR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ESAI_xFCR_xFR		(1 << ESAI_xFCR_xFR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ESAI_xFCR_xFEN_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ESAI_xFCR_xFEN_MASK	(1 << ESAI_xFCR_xFEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ESAI_xFCR_xFEN		(1 << ESAI_xFCR_xFEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * Transmit FIFO Status Register -- REG_ESAI_TFSR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * Receive FIFO Status Register --REG_ESAI_RFSR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ESAI_xFSR_NTFO_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ESAI_xFSR_NRFI_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ESAI_xFSR_NTFI_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ESAI_xFSR_NRFO_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ESAI_xFSR_NTFx_WIDTH	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ESAI_xFSR_NRFx_WIDTH	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ESAI_xFSR_NTFO_MASK	(((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ESAI_xFSR_NTFI_MASK	(((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ESAI_xFSR_NRFO_MASK	(((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ESAI_xFSR_NRFI_MASK	(((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ESAI_xFSR_xFCNT_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ESAI_xFSR_xFCNT_WIDTH	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ESAI_xFSR_xFCNT_MASK	(((1 << ESAI_xFSR_xFCNT_WIDTH) - 1) << ESAI_xFSR_xFCNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* ESAI Transmit Slot Register -- REG_ESAI_TSR 0x98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ESAI_TSR_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ESAI_TSR_WIDTH		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ESAI_TSR_MASK		(((1 << ESAI_TSR_WIDTH) - 1) << ESAI_TSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Serial Audio Interface Status Register -- REG_ESAI_SAISR 0xCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ESAI_SAISR_TODFE_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ESAI_SAISR_TODFE_MASK	(1 << ESAI_SAISR_TODFE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ESAI_SAISR_TODFE	(1 << ESAI_SAISR_TODFE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ESAI_SAISR_TEDE_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ESAI_SAISR_TEDE_MASK	(1 << ESAI_SAISR_TEDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ESAI_SAISR_TEDE		(1 << ESAI_SAISR_TEDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ESAI_SAISR_TDE_SHIFT	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ESAI_SAISR_TDE_MASK	(1 << ESAI_SAISR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ESAI_SAISR_TDE		(1 << ESAI_SAISR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ESAI_SAISR_TUE_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ESAI_SAISR_TUE_MASK	(1 << ESAI_SAISR_TUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ESAI_SAISR_TUE		(1 << ESAI_SAISR_TUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ESAI_SAISR_TFS_SHIFT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ESAI_SAISR_TFS_MASK	(1 << ESAI_SAISR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ESAI_SAISR_TFS		(1 << ESAI_SAISR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ESAI_SAISR_RODF_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ESAI_SAISR_RODF_MASK	(1 << ESAI_SAISR_RODF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ESAI_SAISR_RODF		(1 << ESAI_SAISR_RODF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ESAI_SAISR_REDF_SHIFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ESAI_SAISR_REDF_MASK	(1 << ESAI_SAISR_REDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ESAI_SAISR_REDF		(1 << ESAI_SAISR_REDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ESAI_SAISR_RDF_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ESAI_SAISR_RDF_MASK	(1 << ESAI_SAISR_RDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ESAI_SAISR_RDF		(1 << ESAI_SAISR_RDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ESAI_SAISR_ROE_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ESAI_SAISR_ROE_MASK	(1 << ESAI_SAISR_ROE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ESAI_SAISR_ROE		(1 << ESAI_SAISR_ROE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ESAI_SAISR_RFS_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ESAI_SAISR_RFS_MASK	(1 << ESAI_SAISR_RFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ESAI_SAISR_RFS		(1 << ESAI_SAISR_RFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ESAI_SAISR_IF2_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ESAI_SAISR_IF2_MASK	(1 << ESAI_SAISR_IF2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ESAI_SAISR_IF2		(1 << ESAI_SAISR_IF2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ESAI_SAISR_IF1_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ESAI_SAISR_IF1_MASK	(1 << ESAI_SAISR_IF1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ESAI_SAISR_IF1		(1 << ESAI_SAISR_IF1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ESAI_SAISR_IF0_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ESAI_SAISR_IF0_MASK	(1 << ESAI_SAISR_IF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ESAI_SAISR_IF0		(1 << ESAI_SAISR_IF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Serial Audio Interface Control Register -- REG_ESAI_SAICR 0xD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ESAI_SAICR_ALC_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ESAI_SAICR_ALC_MASK	(1 << ESAI_SAICR_ALC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ESAI_SAICR_ALC		(1 << ESAI_SAICR_ALC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ESAI_SAICR_TEBE_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ESAI_SAICR_TEBE_MASK	(1 << ESAI_SAICR_TEBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ESAI_SAICR_TEBE		(1 << ESAI_SAICR_TEBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ESAI_SAICR_SYNC_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ESAI_SAICR_SYNC_MASK	(1 << ESAI_SAICR_SYNC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ESAI_SAICR_SYNC		(1 << ESAI_SAICR_SYNC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ESAI_SAICR_OF2_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ESAI_SAICR_OF2_MASK	(1 << ESAI_SAICR_OF2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ESAI_SAICR_OF2		(1 << ESAI_SAICR_OF2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ESAI_SAICR_OF1_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ESAI_SAICR_OF1_MASK	(1 << ESAI_SAICR_OF1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ESAI_SAICR_OF1		(1 << ESAI_SAICR_OF1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ESAI_SAICR_OF0_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ESAI_SAICR_OF0_MASK	(1 << ESAI_SAICR_OF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ESAI_SAICR_OF0		(1 << ESAI_SAICR_OF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * Transmit Control Register -- REG_ESAI_TCR 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * Receive Control Register -- REG_ESAI_RCR 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ESAI_xCR_xLIE_SHIFT	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ESAI_xCR_xLIE_MASK	(1 << ESAI_xCR_xLIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ESAI_xCR_xLIE		(1 << ESAI_xCR_xLIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ESAI_xCR_xIE_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ESAI_xCR_xIE_MASK	(1 << ESAI_xCR_xIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ESAI_xCR_xIE		(1 << ESAI_xCR_xIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ESAI_xCR_xEDIE_SHIFT	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ESAI_xCR_xEDIE_MASK	(1 << ESAI_xCR_xEDIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ESAI_xCR_xEDIE		(1 << ESAI_xCR_xEDIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ESAI_xCR_xEIE_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ESAI_xCR_xEIE_MASK	(1 << ESAI_xCR_xEIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ESAI_xCR_xEIE		(1 << ESAI_xCR_xEIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ESAI_xCR_xPR_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ESAI_xCR_xPR_MASK	(1 << ESAI_xCR_xPR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ESAI_xCR_xPR		(1 << ESAI_xCR_xPR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ESAI_xCR_PADC_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ESAI_xCR_PADC_MASK	(1 << ESAI_xCR_PADC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ESAI_xCR_PADC		(1 << ESAI_xCR_PADC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ESAI_xCR_xFSR_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ESAI_xCR_xFSR_MASK	(1 << ESAI_xCR_xFSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ESAI_xCR_xFSR		(1 << ESAI_xCR_xFSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ESAI_xCR_xFSL_SHIFT	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ESAI_xCR_xFSL_MASK	(1 << ESAI_xCR_xFSL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ESAI_xCR_xFSL		(1 << ESAI_xCR_xFSL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ESAI_xCR_xSWS_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ESAI_xCR_xSWS_WIDTH	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ESAI_xCR_xSWS_MASK	(((1 << ESAI_xCR_xSWS_WIDTH) - 1) << ESAI_xCR_xSWS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ESAI_xCR_xSWS(s, w)	((w < 24 ? (s - w + ((w - 8) >> 2)) : (s < 32 ? 0x1e : 0x1f)) << ESAI_xCR_xSWS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ESAI_xCR_xMOD_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ESAI_xCR_xMOD_WIDTH	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ESAI_xCR_xMOD_MASK	(((1 << ESAI_xCR_xMOD_WIDTH) - 1) << ESAI_xCR_xMOD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ESAI_xCR_xMOD_ONDEMAND	(0x1 << ESAI_xCR_xMOD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ESAI_xCR_xMOD_NETWORK	(0x1 << ESAI_xCR_xMOD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ESAI_xCR_xMOD_AC97	(0x3 << ESAI_xCR_xMOD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ESAI_xCR_xWA_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ESAI_xCR_xWA_MASK	(1 << ESAI_xCR_xWA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ESAI_xCR_xWA		(1 << ESAI_xCR_xWA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ESAI_xCR_xSHFD_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ESAI_xCR_xSHFD_MASK	(1 << ESAI_xCR_xSHFD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ESAI_xCR_xSHFD		(1 << ESAI_xCR_xSHFD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ESAI_xCR_xE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ESAI_xCR_TE_WIDTH	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ESAI_xCR_RE_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ESAI_xCR_TE_MASK	(((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ESAI_xCR_RE_MASK	(((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ESAI_xCR_TE(x) 		((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - x)) & ESAI_xCR_TE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ESAI_xCR_RE(x) 		((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - x)) & ESAI_xCR_RE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * Receive Clock Control Register -- REG_ESAI_RCCR 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ESAI_xCCR_xHCKD_SHIFT	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ESAI_xCCR_xHCKD_MASK	(1 << ESAI_xCCR_xHCKD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ESAI_xCCR_xHCKD		(1 << ESAI_xCCR_xHCKD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ESAI_xCCR_xFSD_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ESAI_xCCR_xFSD_MASK	(1 << ESAI_xCCR_xFSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ESAI_xCCR_xFSD		(1 << ESAI_xCCR_xFSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ESAI_xCCR_xCKD_SHIFT	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ESAI_xCCR_xCKD_MASK	(1 << ESAI_xCCR_xCKD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ESAI_xCCR_xCKD		(1 << ESAI_xCCR_xCKD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ESAI_xCCR_xHCKP_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ESAI_xCCR_xHCKP_MASK	(1 << ESAI_xCCR_xHCKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ESAI_xCCR_xHCKP		(1 << ESAI_xCCR_xHCKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ESAI_xCCR_xFSP_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ESAI_xCCR_xFSP_MASK	(1 << ESAI_xCCR_xFSP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ESAI_xCCR_xFSP		(1 << ESAI_xCCR_xFSP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ESAI_xCCR_xCKP_SHIFT	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ESAI_xCCR_xCKP_MASK	(1 << ESAI_xCCR_xCKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ESAI_xCCR_xCKP		(1 << ESAI_xCCR_xCKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ESAI_xCCR_xFP_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ESAI_xCCR_xFP_WIDTH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ESAI_xCCR_xFP_MASK	(((1 << ESAI_xCCR_xFP_WIDTH) - 1) << ESAI_xCCR_xFP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ESAI_xCCR_xFP(v)	((((v) - 1) << ESAI_xCCR_xFP_SHIFT) & ESAI_xCCR_xFP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ESAI_xCCR_xDC_SHIFT     9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ESAI_xCCR_xDC_WIDTH	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ESAI_xCCR_xDC_MASK	(((1 << ESAI_xCCR_xDC_WIDTH) - 1) << ESAI_xCCR_xDC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ESAI_xCCR_xDC(v)	((((v) - 1) << ESAI_xCCR_xDC_SHIFT) & ESAI_xCCR_xDC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ESAI_xCCR_xPSR_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ESAI_xCCR_xPSR_MASK	(1 << ESAI_xCCR_xPSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ESAI_xCCR_xPSR_BYPASS	(1 << ESAI_xCCR_xPSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ESAI_xCCR_xPSR_DIV8	(0 << ESAI_xCCR_xPSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ESAI_xCCR_xPM_SHIFT     0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ESAI_xCCR_xPM_WIDTH     8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ESAI_xCCR_xPM_MASK	(((1 << ESAI_xCCR_xPM_WIDTH) - 1) << ESAI_xCCR_xPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ESAI_xCCR_xPM(v)	((((v) - 1) << ESAI_xCCR_xPM_SHIFT) & ESAI_xCCR_xPM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Transmit Slot Mask Register A/B -- REG_ESAI_TSMA/B 0xE4 ~ 0xF0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ESAI_xSMA_xS_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ESAI_xSMA_xS_WIDTH	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define ESAI_xSMA_xS_MASK	(((1 << ESAI_xSMA_xS_WIDTH) - 1) << ESAI_xSMA_xS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ESAI_xSMA_xS(v)		((v) & ESAI_xSMA_xS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ESAI_xSMB_xS_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ESAI_xSMB_xS_WIDTH	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ESAI_xSMB_xS_MASK	(((1 << ESAI_xSMB_xS_WIDTH) - 1) << ESAI_xSMB_xS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ESAI_xSMB_xS(v)		(((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Port C Direction Register -- REG_ESAI_PRRC 0xF8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ESAI_PRRC_PDC_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ESAI_PRRC_PDC_WIDTH	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ESAI_PRRC_PDC_MASK	(((1 << ESAI_PRRC_PDC_WIDTH) - 1) << ESAI_PRRC_PDC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ESAI_PRRC_PDC(v)	((v) & ESAI_PRRC_PDC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Port C Control Register -- REG_ESAI_PCRC 0xFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ESAI_PCRC_PC_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ESAI_PCRC_PC_WIDTH	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ESAI_PCRC_PC_MASK	(((1 << ESAI_PCRC_PC_WIDTH) - 1) << ESAI_PCRC_PC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ESAI_PCRC_PC(v)		((v) & ESAI_PCRC_PC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ESAI_GPIO		0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* ESAI clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ESAI_HCKT_FSYS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ESAI_HCKT_EXTAL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ESAI_HCKR_FSYS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ESAI_HCKR_EXTAL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* ESAI clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ESAI_TX_DIV_PSR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ESAI_TX_DIV_PM		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ESAI_TX_DIV_FP		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ESAI_RX_DIV_PSR		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ESAI_RX_DIV_PM		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ESAI_RX_DIV_FP		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif /* _FSL_ESAI_DAI_H */