^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _FSL_EASRC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _FSL_EASRC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/asound.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "fsl_asrc_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* EASRC Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* ASRC Input Write FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* ASRC Output Read FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* ASRC Context Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* ASRC Context Control Extended 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* ASRC Context Control Extended 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* ASRC Control Input Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* ASRC Datapath Processor Control Slot0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_EASRC_DPCS0R2(ctx) (0x080 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_EASRC_DPCS0R3(ctx) (0x090 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* ASRC Datapath Processor Control Slot1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_EASRC_DPCS1R0(ctx) (0x0A0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_EASRC_DPCS1R1(ctx) (0x0B0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_EASRC_DPCS1R2(ctx) (0x0C0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_EASRC_DPCS1R3(ctx) (0x0D0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* ASRC Context Output Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_EASRC_COC(ctx) (0x0E0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ASRC Control Output Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_EASRC_COA(ctx) (0x0F0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* ASRC Sample FIFO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_EASRC_SFS(ctx) (0x100 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* ASRC Resampling Ratio Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_EASRC_RRL(ctx) (0x110 + 8 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ASRC Resampling Ratio High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_EASRC_RRH(ctx) (0x114 + 8 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ASRC Resampling Ratio Update Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_EASRC_RUC(ctx) (0x130 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* ASRC Resampling Ratio Update Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_EASRC_RUR(ctx) (0x140 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* ASRC Resampling Center Tap Coefficient Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_EASRC_RCTCL (0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* ASRC Resampling Center Tap Coefficient High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_EASRC_RCTCH (0x154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* ASRC Prefilter Coefficient FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_EASRC_PCF(ctx) (0x160 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* ASRC Context Resampling Coefficient Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_EASRC_CRCM 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* ASRC Context Resampling Coefficient Control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_EASRC_CRCC 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ASRC Interrupt Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_EASRC_IRQC 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* ASRC Interrupt Status Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_EASRC_IRQF 0x17C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* ASRC Channel Status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_EASRC_CS0(ctx) (0x180 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* ASRC Channel Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_EASRC_CS1(ctx) (0x190 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ASRC Channel Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_EASRC_CS2(ctx) (0x1A0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ASRC Channel Status 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_EASRC_CS3(ctx) (0x1B0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ASRC Channel Status 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_EASRC_CS4(ctx) (0x1C0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* ASRC Channel Status 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_EASRC_CS5(ctx) (0x1D0 + 4 * (ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* ASRC Debug Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_EASRC_DBGC 0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* ASRC Debug Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_EASRC_DBGS 0x1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_EASRC_FIFO(x, ctx) (x == IN ? REG_EASRC_WRFIFO(ctx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) : REG_EASRC_RDFIFO(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* ASRC Context Control (CC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EASRC_CC_EN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EASRC_CC_STOP_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EASRC_CC_FWMDE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EASRC_CC_FIFO_WTMK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EASRC_CC_FIFO_WTMK_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) << EASRC_CC_FIFO_WTMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) & EASRC_CC_FIFO_WTMK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EASRC_CC_SAMPLE_POS_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EASRC_CC_SAMPLE_POS_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EASRC_CC_SAMPLE_POS_MASK ((BIT(EASRC_CC_SAMPLE_POS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) << EASRC_CC_SAMPLE_POS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EASRC_CC_SAMPLE_POS(v) (((v) << EASRC_CC_SAMPLE_POS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) & EASRC_CC_SAMPLE_POS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EASRC_CC_ENDIANNESS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EASRC_CC_ENDIANNESS_MASK BIT(EASRC_CC_ENDIANNESS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EASRC_CC_ENDIANNESS BIT(EASRC_CC_ENDIANNESS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EASRC_CC_BPS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EASRC_CC_BPS_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EASRC_CC_BPS_MASK ((BIT(EASRC_CC_BPS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) << EASRC_CC_BPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EASRC_CC_BPS(v) (((v) << EASRC_CC_BPS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) & EASRC_CC_BPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EASRC_CC_FMT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EASRC_CC_FMT_MASK BIT(EASRC_CC_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EASRC_CC_FMT BIT(EASRC_CC_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EASRC_CC_INSIGN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EASRC_CC_INSIGN_MASK BIT(EASRC_CC_INSIGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EASRC_CC_INSIGN BIT(EASRC_CC_INSIGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EASRC_CC_CHEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EASRC_CC_CHEN_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EASRC_CC_CHEN_MASK ((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) << EASRC_CC_CHEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EASRC_CC_CHEN(v) (((v) << EASRC_CC_CHEN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) & EASRC_CC_CHEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* ASRC Context Control Extended 1 (CCE1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EASRC_CCE1_COEF_WS_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EASRC_CCE1_COEF_WS_MASK BIT(EASRC_CCE1_COEF_WS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EASRC_CCE1_COEF_WS BIT(EASRC_CCE1_COEF_WS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EASRC_CCE1_COEF_MEM_RST_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EASRC_CCE1_COEF_MEM_RST_MASK BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EASRC_CCE1_COEF_MEM_RST BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EASRC_CCE1_PF_EXP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EASRC_CCE1_PF_EXP_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EASRC_CCE1_PF_EXP_MASK ((BIT(EASRC_CCE1_PF_EXP_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) << EASRC_CCE1_PF_EXP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EASRC_CCE1_PF_EXP(v) (((v) << EASRC_CCE1_PF_EXP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) & EASRC_CCE1_PF_EXP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EASRC_CCE1_PF_ST1_WBFP_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EASRC_CCE1_PF_ST1_WBFP_MASK BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EASRC_CCE1_PF_ST1_WBFP BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EASRC_CCE1_PF_TSEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EASRC_CCE1_PF_TSEN_MASK BIT(EASRC_CCE1_PF_TSEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EASRC_CCE1_PF_TSEN BIT(EASRC_CCE1_PF_TSEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EASRC_CCE1_RS_BYPASS_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EASRC_CCE1_RS_BYPASS_MASK BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EASRC_CCE1_RS_BYPASS BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EASRC_CCE1_PF_BYPASS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EASRC_CCE1_PF_BYPASS_MASK BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EASRC_CCE1_PF_BYPASS BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EASRC_CCE1_RS_STOP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EASRC_CCE1_RS_STOP_MASK BIT(EASRC_CCE1_RS_STOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EASRC_CCE1_RS_STOP BIT(EASRC_CCE1_RS_STOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EASRC_CCE1_PF_STOP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EASRC_CCE1_PF_STOP_MASK BIT(EASRC_CCE1_PF_STOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EASRC_CCE1_PF_STOP BIT(EASRC_CCE1_PF_STOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EASRC_CCE1_RS_INIT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EASRC_CCE1_RS_INIT_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EASRC_CCE1_RS_INIT_MASK ((BIT(EASRC_CCE1_RS_INIT_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) << EASRC_CCE1_RS_INIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EASRC_CCE1_RS_INIT(v) (((v) << EASRC_CCE1_RS_INIT_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) & EASRC_CCE1_RS_INIT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EASRC_CCE1_PF_INIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EASRC_CCE1_PF_INIT_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EASRC_CCE1_PF_INIT_MASK ((BIT(EASRC_CCE1_PF_INIT_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) << EASRC_CCE1_PF_INIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EASRC_CCE1_PF_INIT(v) (((v) << EASRC_CCE1_PF_INIT_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) & EASRC_CCE1_PF_INIT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* ASRC Context Control Extended 2 (CCE2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EASRC_CCE2_ST2_TAPS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EASRC_CCE2_ST2_TAPS_WIDTH 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EASRC_CCE2_ST2_TAPS_MASK ((BIT(EASRC_CCE2_ST2_TAPS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) << EASRC_CCE2_ST2_TAPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EASRC_CCE2_ST2_TAPS(v) (((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) & EASRC_CCE2_ST2_TAPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EASRC_CCE2_ST1_TAPS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EASRC_CCE2_ST1_TAPS_WIDTH 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EASRC_CCE2_ST1_TAPS_MASK ((BIT(EASRC_CCE2_ST1_TAPS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) << EASRC_CCE2_ST1_TAPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EASRC_CCE2_ST1_TAPS(v) (((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) & EASRC_CCE2_ST1_TAPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* ASRC Control Input Access (CIA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EASRC_CIA_ITER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EASRC_CIA_ITER_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EASRC_CIA_ITER_MASK ((BIT(EASRC_CIA_ITER_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) << EASRC_CIA_ITER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EASRC_CIA_ITER(v) (((v) << EASRC_CIA_ITER_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) & EASRC_CIA_ITER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EASRC_CIA_GRLEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EASRC_CIA_GRLEN_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EASRC_CIA_GRLEN_MASK ((BIT(EASRC_CIA_GRLEN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) << EASRC_CIA_GRLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EASRC_CIA_GRLEN(v) (((v) << EASRC_CIA_GRLEN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) & EASRC_CIA_GRLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EASRC_CIA_ACCLEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EASRC_CIA_ACCLEN_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EASRC_CIA_ACCLEN_MASK ((BIT(EASRC_CIA_ACCLEN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) << EASRC_CIA_ACCLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EASRC_CIA_ACCLEN(v) (((v) << EASRC_CIA_ACCLEN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) & EASRC_CIA_ACCLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* ASRC Datapath Processor Control Slot0 Register0 (DPCS0R0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EASRC_DPCS0R0_MAXCH_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EASRC_DPCS0R0_MAXCH_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EASRC_DPCS0R0_MAXCH_MASK ((BIT(EASRC_DPCS0R0_MAXCH_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) << EASRC_DPCS0R0_MAXCH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EASRC_DPCS0R0_MAXCH(v) (((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) & EASRC_DPCS0R0_MAXCH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EASRC_DPCS0R0_MINCH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EASRC_DPCS0R0_MINCH_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define EASRC_DPCS0R0_MINCH_MASK ((BIT(EASRC_DPCS0R0_MINCH_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) << EASRC_DPCS0R0_MINCH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EASRC_DPCS0R0_MINCH(v) (((v) << EASRC_DPCS0R0_MINCH_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) & EASRC_DPCS0R0_MINCH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EASRC_DPCS0R0_NUMCH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EASRC_DPCS0R0_NUMCH_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EASRC_DPCS0R0_NUMCH_MASK ((BIT(EASRC_DPCS0R0_NUMCH_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) << EASRC_DPCS0R0_NUMCH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EASRC_DPCS0R0_NUMCH(v) (((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) & EASRC_DPCS0R0_NUMCH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define EASRC_DPCS0R0_CTXNUM_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define EASRC_DPCS0R0_CTXNUM_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define EASRC_DPCS0R0_CTXNUM_MASK ((BIT(EASRC_DPCS0R0_CTXNUM_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) << EASRC_DPCS0R0_CTXNUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define EASRC_DPCS0R0_CTXNUM(v) (((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) & EASRC_DPCS0R0_CTXNUM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define EASRC_DPCS0R0_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define EASRC_DPCS0R0_EN_MASK BIT(EASRC_DPCS0R0_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EASRC_DPCS0R0_EN BIT(EASRC_DPCS0R0_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* ASRC Datapath Processor Control Slot0 Register1 (DPCS0R1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define EASRC_DPCS0R1_ST1_EXP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EASRC_DPCS0R1_ST1_EXP_WIDTH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define EASRC_DPCS0R1_ST1_EXP_MASK ((BIT(EASRC_DPCS0R1_ST1_EXP_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) << EASRC_DPCS0R1_ST1_EXP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define EASRC_DPCS0R1_ST1_EXP(v) (((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) & EASRC_DPCS0R1_ST1_EXP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* ASRC Datapath Processor Control Slot0 Register2 (DPCS0R2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EASRC_DPCS0R2_ST1_MA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EASRC_DPCS0R2_ST1_MA_WIDTH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EASRC_DPCS0R2_ST1_MA_MASK ((BIT(EASRC_DPCS0R2_ST1_MA_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) << EASRC_DPCS0R2_ST1_MA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EASRC_DPCS0R2_ST1_MA(v) (((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) & EASRC_DPCS0R2_ST1_MA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EASRC_DPCS0R2_ST1_SA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EASRC_DPCS0R2_ST1_SA_WIDTH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define EASRC_DPCS0R2_ST1_SA_MASK ((BIT(EASRC_DPCS0R2_ST1_SA_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) << EASRC_DPCS0R2_ST1_SA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EASRC_DPCS0R2_ST1_SA(v) (((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) & EASRC_DPCS0R2_ST1_SA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* ASRC Datapath Processor Control Slot0 Register3 (DPCS0R3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define EASRC_DPCS0R3_ST2_MA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EASRC_DPCS0R3_ST2_MA_WIDTH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define EASRC_DPCS0R3_ST2_MA_MASK ((BIT(EASRC_DPCS0R3_ST2_MA_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) << EASRC_DPCS0R3_ST2_MA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define EASRC_DPCS0R3_ST2_MA(v) (((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) & EASRC_DPCS0R3_ST2_MA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define EASRC_DPCS0R3_ST2_SA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EASRC_DPCS0R3_ST2_SA_WIDTH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EASRC_DPCS0R3_ST2_SA_MASK ((BIT(EASRC_DPCS0R3_ST2_SA_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) << EASRC_DPCS0R3_ST2_SA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define EASRC_DPCS0R3_ST2_SA(v) (((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) & EASRC_DPCS0R3_ST2_SA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* ASRC Context Output Control (COC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define EASRC_COC_FWMDE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EASRC_COC_FWMDE_MASK BIT(EASRC_COC_FWMDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define EASRC_COC_FWMDE BIT(EASRC_COC_FWMDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define EASRC_COC_FIFO_WTMK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define EASRC_COC_FIFO_WTMK_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EASRC_COC_FIFO_WTMK_MASK ((BIT(EASRC_COC_FIFO_WTMK_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) << EASRC_COC_FIFO_WTMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define EASRC_COC_FIFO_WTMK(v) (((v) << EASRC_COC_FIFO_WTMK_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) & EASRC_COC_FIFO_WTMK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define EASRC_COC_SAMPLE_POS_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define EASRC_COC_SAMPLE_POS_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define EASRC_COC_SAMPLE_POS_MASK ((BIT(EASRC_COC_SAMPLE_POS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) << EASRC_COC_SAMPLE_POS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define EASRC_COC_SAMPLE_POS(v) (((v) << EASRC_COC_SAMPLE_POS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) & EASRC_COC_SAMPLE_POS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define EASRC_COC_ENDIANNESS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define EASRC_COC_ENDIANNESS_MASK BIT(EASRC_COC_ENDIANNESS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define EASRC_COC_ENDIANNESS BIT(EASRC_COC_ENDIANNESS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define EASRC_COC_BPS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define EASRC_COC_BPS_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define EASRC_COC_BPS_MASK ((BIT(EASRC_COC_BPS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) << EASRC_COC_BPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define EASRC_COC_BPS(v) (((v) << EASRC_COC_BPS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) & EASRC_COC_BPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define EASRC_COC_FMT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define EASRC_COC_FMT_MASK BIT(EASRC_COC_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EASRC_COC_FMT BIT(EASRC_COC_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define EASRC_COC_OUTSIGN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define EASRC_COC_OUTSIGN_MASK BIT(EASRC_COC_OUTSIGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define EASRC_COC_OUTSIGN_OUT BIT(EASRC_COC_OUTSIGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define EASRC_COC_IEC_VDATA_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define EASRC_COC_IEC_VDATA_MASK BIT(EASRC_COC_IEC_VDATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define EASRC_COC_IEC_VDATA BIT(EASRC_COC_IEC_VDATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define EASRC_COC_IEC_EN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define EASRC_COC_IEC_EN_MASK BIT(EASRC_COC_IEC_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define EASRC_COC_IEC_EN BIT(EASRC_COC_IEC_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define EASRC_COC_DITHER_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define EASRC_COC_DITHER_EN_MASK BIT(EASRC_COC_DITHER_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define EASRC_COC_DITHER_EN BIT(EASRC_COC_DITHER_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* ASRC Control Output Access (COA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define EASRC_COA_ITER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define EASRC_COA_ITER_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define EASRC_COA_ITER_MASK ((BIT(EASRC_COA_ITER_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) << EASRC_COA_ITER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define EASRC_COA_ITER(v) (((v) << EASRC_COA_ITER_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) & EASRC_COA_ITER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define EASRC_COA_GRLEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define EASRC_COA_GRLEN_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define EASRC_COA_GRLEN_MASK ((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) << EASRC_COA_GRLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define EASRC_COA_GRLEN(v) (((v) << EASRC_COA_GRLEN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) & EASRC_COA_GRLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define EASRC_COA_ACCLEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define EASRC_COA_ACCLEN_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define EASRC_COA_ACCLEN_MASK ((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) << EASRC_COA_ACCLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define EASRC_COA_ACCLEN(v) (((v) << EASRC_COA_ACCLEN_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) & EASRC_COA_ACCLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* ASRC Sample FIFO Status (SFS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define EASRC_SFS_IWTMK_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define EASRC_SFS_IWTMK_MASK BIT(EASRC_SFS_IWTMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define EASRC_SFS_IWTMK BIT(EASRC_SFS_IWTMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define EASRC_SFS_NSGI_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EASRC_SFS_NSGI_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EASRC_SFS_NSGI_MASK ((BIT(EASRC_SFS_NSGI_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) << EASRC_SFS_NSGI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define EASRC_SFS_NSGI(v) (((v) << EASRC_SFS_NSGI_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) & EASRC_SFS_NSGI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define EASRC_SFS_OWTMK_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define EASRC_SFS_OWTMK_MASK BIT(EASRC_SFS_OWTMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define EASRC_SFS_OWTMK BIT(EASRC_SFS_OWTMK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define EASRC_SFS_NSGO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EASRC_SFS_NSGO_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define EASRC_SFS_NSGO_MASK ((BIT(EASRC_SFS_NSGO_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) << EASRC_SFS_NSGO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define EASRC_SFS_NSGO(v) (((v) << EASRC_SFS_NSGO_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) & EASRC_SFS_NSGO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* ASRC Resampling Ratio Low (RRL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define EASRC_RRL_RS_RL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EASRC_RRL_RS_RL_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define EASRC_RRL_RS_RL(v) ((v) << EASRC_RRL_RS_RL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* ASRC Resampling Ratio High (RRH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EASRC_RRH_RS_VLD_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EASRC_RRH_RS_VLD_MASK BIT(EASRC_RRH_RS_VLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define EASRC_RRH_RS_VLD BIT(EASRC_RRH_RS_VLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define EASRC_RRH_RS_RH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define EASRC_RRH_RS_RH_WIDTH 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define EASRC_RRH_RS_RH_MASK ((BIT(EASRC_RRH_RS_RH_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) << EASRC_RRH_RS_RH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define EASRC_RRH_RS_RH(v) (((v) << EASRC_RRH_RS_RH_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) & EASRC_RRH_RS_RH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* ASRC Resampling Ratio Update Control (RSUC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define EASRC_RSUC_RS_RM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define EASRC_RSUC_RS_RM_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define EASRC_RSUC_RS_RM(v) ((v) << EASRC_RSUC_RS_RM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* ASRC Resampling Ratio Update Rate (RRUR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EASRC_RRUR_RRR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define EASRC_RRUR_RRR_WIDTH 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define EASRC_RRUR_RRR_MASK ((BIT(EASRC_RRUR_RRR_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) << EASRC_RRUR_RRR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define EASRC_RRUR_RRR(v) (((v) << EASRC_RRUR_RRR_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) & EASRC_RRUR_RRR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* ASRC Resampling Center Tap Coefficient Low (RCTCL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define EASRC_RCTCL_RS_CL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define EASRC_RCTCL_RS_CL_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define EASRC_RCTCL_RS_CL(v) ((v) << EASRC_RCTCL_RS_CL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* ASRC Resampling Center Tap Coefficient High (RCTCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define EASRC_RCTCH_RS_CH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define EASRC_RCTCH_RS_CH_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define EASRC_RCTCH_RS_CH(v) ((v) << EASRC_RCTCH_RS_CH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* ASRC Prefilter Coefficient FIFO (PCF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define EASRC_PCF_CD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define EASRC_PCF_CD_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define EASRC_PCF_CD(v) ((v) << EASRC_PCF_CD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* ASRC Context Resampling Coefficient Memory (CRCM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define EASRC_CRCM_RS_CWD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define EASRC_CRCM_RS_CWD_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define EASRC_CRCM_RS_CWD(v) ((v) << EASRC_CRCM_RS_CWD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* ASRC Context Resampling Coefficient Control (CRCC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define EASRC_CRCC_RS_CA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define EASRC_CRCC_RS_CA_WIDTH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define EASRC_CRCC_RS_CA_MASK ((BIT(EASRC_CRCC_RS_CA_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) << EASRC_CRCC_RS_CA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define EASRC_CRCC_RS_CA(v) (((v) << EASRC_CRCC_RS_CA_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) & EASRC_CRCC_RS_CA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define EASRC_CRCC_RS_TAPS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define EASRC_CRCC_RS_TAPS_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define EASRC_CRCC_RS_TAPS_MASK ((BIT(EASRC_CRCC_RS_TAPS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) << EASRC_CRCC_RS_TAPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define EASRC_CRCC_RS_TAPS(v) (((v) << EASRC_CRCC_RS_TAPS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) & EASRC_CRCC_RS_TAPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define EASRC_CRCC_RS_CPR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define EASRC_CRCC_RS_CPR_MASK BIT(EASRC_CRCC_RS_CPR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define EASRC_CRCC_RS_CPR BIT(EASRC_CRCC_RS_CPR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* ASRC Interrupt_Control (IC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define EASRC_IRQC_RSDM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define EASRC_IRQC_RSDM_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define EASRC_IRQC_RSDM_MASK ((BIT(EASRC_IRQC_RSDM_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) << EASRC_IRQC_RSDM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define EASRC_IRQC_RSDM(v) (((v) << EASRC_IRQC_RSDM_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) & EASRC_IRQC_RSDM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define EASRC_IRQC_OERM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define EASRC_IRQC_OERM_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define EASRC_IRQC_OERM_MASK ((BIT(EASRC_IRQC_OERM_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) << EASRC_IRQC_OERM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define EASRC_IRQC_OERM(v) (((v) << EASRC_IRQC_OERM_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) & EASRC_IEQC_OERM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define EASRC_IRQC_IOM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define EASRC_IRQC_IOM_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define EASRC_IRQC_IOM_MASK ((BIT(EASRC_IRQC_IOM_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) << EASRC_IRQC_IOM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define EASRC_IRQC_IOM(v) (((v) << EASRC_IRQC_IOM_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) & EASRC_IRQC_IOM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* ASRC Interrupt Status Flags (ISF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define EASRC_IRQF_RSD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define EASRC_IRQF_RSD_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define EASRC_IRQF_RSD_MASK ((BIT(EASRC_IRQF_RSD_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) << EASRC_IRQF_RSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define EASRC_IRQF_RSD(v) (((v) << EASRC_IRQF_RSD_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) & EASRC_IRQF_RSD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define EASRC_IRQF_OER_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define EASRC_IRQF_OER_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define EASRC_IRQF_OER_MASK ((BIT(EASRC_IRQF_OER_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) << EASRC_IRQF_OER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define EASRC_IRQF_OER(v) (((v) << EASRC_IRQF_OER_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) & EASRC_IRQF_OER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define EASRC_IRQF_IFO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define EASRC_IRQF_IFO_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define EASRC_IRQF_IFO_MASK ((BIT(EASRC_IRQF_IFO_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) << EASRC_IRQF_IFO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define EASRC_IRQF_IFO(v) (((v) << EASRC_IRQF_IFO_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) & EASRC_IRQF_IFO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* ASRC Context Channel STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define EASRC_CSx_CSx_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define EASRC_CSx_CSx_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define EASRC_CSx_CSx(v) ((v) << EASRC_CSx_CSx_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* ASRC Debug Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define EASRC_DBGC_DMS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define EASRC_DBGC_DMS_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define EASRC_DBGC_DMS_MASK ((BIT(EASRC_DBGC_DMS_WIDTH) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) << EASRC_DBGC_DMS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define EASRC_DBGC_DMS(v) (((v) << EASRC_DBGC_DMS_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) & EASRC_DBGC_DMS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* ASRC Debug Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define EASRC_DBGS_DS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define EASRC_DBGS_DS_WIDTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define EASRC_DBGS_DS(v) ((v) << EASRC_DBGS_DS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* General Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define EASRC_CTX_MAX_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define EASRC_RS_COEFF_MEM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define EASRC_PF_COEFF_MEM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Prefilter constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define EASRC_PF_ST1_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define EASRC_PF_TWO_STAGE_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define EASRC_PF_ST1_COEFF_WR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define EASRC_PF_ST2_COEFF_WR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define EASRC_MAX_PF_TAPS 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Resampling constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define EASRC_RS_32_TAPS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define EASRC_RS_64_TAPS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define EASRC_RS_128_TAPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Initialization mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define EASRC_INIT_MODE_SW_CONTROL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define EASRC_INIT_MODE_REPLICATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define EASRC_INIT_MODE_ZERO_FILL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* FIFO watermarks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define FSL_EASRC_INPUTFIFO_WML 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define FSL_EASRC_OUTPUTFIFO_WML 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define EASRC_INPUTFIFO_THRESHOLD_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define EASRC_INPUTFIFO_THRESHOLD_MAX 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define EASRC_OUTPUTFIFO_THRESHOLD_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define EASRC_OUTPUTFIFO_THRESHOLD_MAX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define EASRC_DMA_BUFFER_SIZE (1024 * 48 * 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define EASRC_MAX_BUFFER_SIZE (1024 * 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define FIRMWARE_MAGIC 0xDEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FIRMWARE_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define PREFILTER_MEM_LEN 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum easrc_word_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) EASRC_WIDTH_16_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) EASRC_WIDTH_20_BIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) EASRC_WIDTH_24_BIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) EASRC_WIDTH_32_BIT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct __attribute__((__packed__)) asrc_firmware_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 interp_scen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 prefil_scen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 firmware_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct __attribute__((__packed__)) interp_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 num_phases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u64 center_tap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u64 coeff[8192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct __attribute__((__packed__)) prefil_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 insr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 outsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 st1_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 st2_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 st1_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u64 coeff[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct dma_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) void *dma_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned int max_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct fsl_easrc_data_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int width : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int endianness : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int unsign : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned int floating_point : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int iec958: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int sample_pos: 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int addexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct fsl_easrc_io_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct fsl_easrc_data_fmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int group_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int iterations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int access_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned int fifo_wtmk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned int sample_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int norm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct fsl_easrc_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bool busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int ctx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int slot_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int num_channel; /* maximum is 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int min_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int max_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int pf_mem_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * fsl_easrc_ctx_priv: EASRC context private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * @in_params: input parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * @out_params: output parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * @st1_num_taps: tap number of stage 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * @st2_num_taps: tap number of stage 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @st1_num_exp: exponent number of stage 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @pf_init_mode: prefilter init mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * @rs_init_mode: resample filter init mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @ctx_streams: stream flag of ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * @rs_ratio: resampler ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * @st1_coeff: pointer of stage 1 coeff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * @st2_coeff: pointer of stage 2 coeff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * @in_filled_sample: input filled sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @out_missed_sample: sample missed in output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @st1_addexp: exponent added for stage1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @st2_addexp: exponent added for stage2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct fsl_easrc_ctx_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct fsl_easrc_io_params in_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct fsl_easrc_io_params out_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int st1_num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int st2_num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int st1_num_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned int pf_init_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int rs_init_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int ctx_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u64 rs_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u64 *st1_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u64 *st2_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int in_filled_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int out_missed_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int st1_addexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int st2_addexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * fsl_easrc_priv: EASRC private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @slot: slot setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * @firmware_hdr: the header of firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @interp: pointer to interpolation filter coeff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * @prefil: pointer to prefilter coeff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * @fw: firmware of coeff table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * @fw_name: firmware name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * @rs_num_taps: resample filter taps, 32, 64, or 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * @bps_iec958: bits per sample of iec958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * @rs_coeff: resampler coefficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * @const_coeff: one tap prefilter coefficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * @firmware_loaded: firmware is loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct fsl_easrc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct fsl_easrc_slot slot[EASRC_CTX_MAX_NUM][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct asrc_firmware_hdr *firmware_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct interp_params *interp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct prefil_params *prefil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) const char *fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int rs_num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int bps_iec958[EASRC_CTX_MAX_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u64 *rs_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u64 const_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int firmware_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #endif /* _FSL_EASRC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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