^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "fsl_easrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "imx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SNDRV_PCM_FMTBIT_U16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SNDRV_PCM_FMTBIT_U24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SNDRV_PCM_FMTBIT_U24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SNDRV_PCM_FMTBIT_S32_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SNDRV_PCM_FMTBIT_U32_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SNDRV_PCM_FMTBIT_U20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SNDRV_PCM_FMTBIT_FLOAT_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct soc_mreg_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (struct soc_mreg_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int regval = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) easrc_priv->bps_iec958[mc->regbase] = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct soc_mreg_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (struct soc_mreg_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct soc_mreg_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (struct soc_mreg_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regval = snd_soc_component_read(component, mc->regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ucontrol->value.integer.value[0] = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct soc_mreg_control *mc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (struct soc_mreg_control *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int regval = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = snd_soc_component_write(component, mc->regbase, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SOC_SINGLE_REG_RW(xname, xreg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .put = fsl_easrc_set_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .private_value = (unsigned long)&(struct soc_mreg_control) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .regbase = xreg, .regcount = 1, .nbits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .invert = 0, .min = 0, .max = 0xffffffff, } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SOC_SINGLE_VAL_RW(xname, xreg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .put = fsl_easrc_iec958_put_bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .private_value = (unsigned long)&(struct soc_mreg_control) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .regbase = xreg, .regcount = 1, .nbits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .invert = 0, .min = 0, .max = 2, } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * fsl_easrc_set_rs_ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * According to the resample taps, calculate the resample ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * ratio = in_rate / out_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int in_rate = ctx_priv->in_params.norm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int out_rate = ctx_priv->out_params.norm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int frac_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) switch (easrc_priv->rs_num_taps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case EASRC_RS_32_TAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* integer bits = 5; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) frac_bits = 39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case EASRC_RS_64_TAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* integer bits = 6; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) frac_bits = 38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case EASRC_RS_128_TAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* integer bits = 7; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) frac_bits = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val = (u64)in_rate << frac_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) do_div(val, out_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) r = (uint32_t *)&val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (r[1] & 0xFFFFF000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(&easrc->pdev->dev, "ratio exceed range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EASRC_RRL_RS_RL(r[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EASRC_RRH_RS_RH(r[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Normalize input and output sample rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct fsl_easrc_ctx_priv *ctx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) a = ctx_priv->in_params.sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) b = ctx_priv->out_params.sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) a = gcd(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Divide by gcd to normalize the rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Resets the pointer of the coeff memory pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int ctx_id, int mem_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) switch (mem_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case EASRC_PF_COEFF_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* This resets the prefilter memory pointer addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ctx_id >= EASRC_CTX_MAX_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dev, "Invalid context id[%d]\n", ctx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg = REG_EASRC_CCE1(ctx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mask = EASRC_CCE1_COEF_MEM_RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val = EASRC_CCE1_COEF_MEM_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case EASRC_RS_COEFF_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* This resets the resampling memory pointer addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) reg = REG_EASRC_CRCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mask = EASRC_CRCC_RS_CPR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val = EASRC_CRCC_RS_CPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(dev, "Unknown memory type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * To reset the write pointer back to zero, the register field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * ASRC_CTX_CTRL_EXT1x[PF_COEFF_MEM_RST] can be toggled from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * 0x0 to 0x1 to 0x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_update_bits(easrc->regmap, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) regmap_update_bits(easrc->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) regmap_update_bits(easrc->regmap, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline uint32_t bits_taps_to_val(unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case EASRC_RS_32_TAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case EASRC_RS_64_TAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case EASRC_RS_128_TAPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int fsl_easrc_resampler_config(struct fsl_asrc *easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct device *dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct interp_params *interp = easrc_priv->interp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct interp_params *selected_interp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int num_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u64 *coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(dev, "firmware not loaded!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) for (i = 0; i < hdr->interp_scen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if ((interp[i].num_taps - 1) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bits_taps_to_val(easrc_priv->rs_num_taps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) coef = interp[i].coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) selected_interp = &interp[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) selected_interp->num_taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) selected_interp->num_phases);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!selected_interp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(dev, "failed to get interpreter configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * RS_LOW - first half of center tap of the sinc function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * RS_HIGH - second half of center tap of the sinc function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * This is due to the fact the resampling function must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * symetrical - i.e. odd number of taps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) r = (uint32_t *)&selected_interp->center_tap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Write Number of Resampling Coefficient Taps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * 00b - 32-Tap Resampling Filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * 01b - 64-Tap Resampling Filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * 10b - 128-Tap Resampling Filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * 11b - N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) regmap_update_bits(easrc->regmap, REG_EASRC_CRCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EASRC_CRCC_RS_TAPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Reset prefilter coefficient pointer back to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * When the filter is programmed to run in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * This means the number of writes is constant no matter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * the mode we are using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) num_coeff = 16 * 128 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (i = 0; i < num_coeff; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) r = (uint32_t *)&coef[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) regmap_write(easrc->regmap, REG_EASRC_CRCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) EASRC_CRCM_RS_CWD(r[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) regmap_write(easrc->regmap, REG_EASRC_CRCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) EASRC_CRCM_RS_CWD(r[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Scale filter coefficients (64 bits float)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * scale it by multiplying filter coefficients by 2^31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * For input int[16, 24, 32] -> output float32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @easrc: Structure pointer of fsl_asrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @infilter : Pointer to non-scaled input filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @shift: The multiply factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @outfilter: scaled filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u64 *infilter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u64 *outfilter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct device *dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u64 coef = *infilter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) s64 exp = (coef & 0x7ff0000000000000ll) >> 52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u64 outcoef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * If exponent is zero (value == 0), or 7ff (value == NaNs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * dont touch the content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (exp == 0 || exp == 0x7ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *outfilter = coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* coef * 2^shift ==> exp + shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) exp += shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(dev, "coef out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *outfilter = outcoef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u64 *coef, int n_taps, int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct device *dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* If STx_NUM_TAPS is set to 0x0 then return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!n_taps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!coef) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(dev, "coef table is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * When switching between stages, the address pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * should be reset back to 0x0 before performing a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = 0; i < (n_taps + 1) / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) r = (uint32_t *)&tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) EASRC_PCF_CD(r[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) EASRC_PCF_CD(r[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int ctx_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct prefil_params *prefil, *selected_prefil = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct fsl_easrc_ctx_priv *ctx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct fsl_easrc_priv *easrc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct asrc_firmware_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct fsl_asrc_pair *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 inrate, outrate, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 in_s_rate, out_s_rate, in_s_fmt, out_s_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ctx_id >= EASRC_CTX_MAX_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(dev, "Invalid context id[%d]\n", ctx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ctx = easrc->pair[ctx_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) in_s_rate = ctx_priv->in_params.sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) out_s_rate = ctx_priv->out_params.sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) in_s_fmt = ctx_priv->in_params.sample_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) out_s_fmt = ctx_priv->out_params.sample_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ctx_priv->st1_num_taps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ctx_priv->st2_num_taps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * The audio float point data range is (-1, 1), the asrc would output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * all zero for float point input and integer output case, that is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * drop the fractional part of the data directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * In order to support float to int conversion or int to float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * conversion we need to do special operation on the coefficient to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * enlarge/reduce the data to the expected range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * For float to int case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Up sampling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * 1. Create a 1 tap filter with center tap (only tap) of 2^31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * in 64 bits floating point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * double value = (double)(((uint64_t)1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * 2. Program 1 tap prefilter with center tap above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Down sampling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * 1. If the filter is single stage filter, add "shift" to the exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * of stage 1 coefficients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * 2. If the filter is two stage filter , add "shift" to the exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * of stage 2 coefficients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * The "shift" is 31, same for int16, int24, int32 case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * For int to float case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Up sampling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * 1. Create a 1 tap filter with center tap (only tap) of 2^-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * in 64 bits floating point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * 2. Program 1 tap prefilter with center tap above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Down sampling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * 1. If the filter is single stage filter, subtract "shift" to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * exponent of stage 1 coefficients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * 2. If the filter is two stage filter , subtract "shift" to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * exponent of stage 2 coefficients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * The "shift" is 15,23,31, different for int16, int24, int32 case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (out_s_rate >= in_s_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (out_s_rate == in_s_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) regmap_update_bits(easrc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) EASRC_CCE1_RS_BYPASS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EASRC_CCE1_RS_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ctx_priv->st1_num_taps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ctx_priv->st1_coeff = &easrc_priv->const_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ctx_priv->st1_num_exp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ctx_priv->st2_num_taps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ctx_priv->st1_addexp = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) inrate = ctx_priv->in_params.norm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) outrate = ctx_priv->out_params.norm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hdr = easrc_priv->firmware_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) prefil = easrc_priv->prefil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (i = 0; i < hdr->prefil_scen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (inrate == prefil[i].insr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) outrate == prefil[i].outsr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) selected_prefil = &prefil[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) selected_prefil->insr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) selected_prefil->outsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) selected_prefil->st1_taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) selected_prefil->st2_taps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!selected_prefil) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) in_s_rate, inrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) out_s_rate, outrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * In prefilter coeff array, first st1_num_taps represent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * stage1 prefilter coefficients followed by next st2_num_taps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * representing stage 2 coefficients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ctx_priv->st1_num_taps = selected_prefil->st1_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ctx_priv->st1_coeff = selected_prefil->coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ctx_priv->st1_num_exp = selected_prefil->st1_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) offset = ((selected_prefil->st1_taps + 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ctx_priv->st2_num_taps = selected_prefil->st2_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ctx_priv->st2_coeff = selected_prefil->coeff + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* only change stage2 coefficient for 2 stage case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ctx_priv->st2_num_taps > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ctx_priv->st2_addexp = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ctx_priv->st1_addexp = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ctx_priv->st2_num_taps > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ctx_priv->st2_num_taps / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ctx_priv->out_missed_sample += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * To modify the value of a prefilter coefficient, the user must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * perform a write to the register ASRC_PRE_COEFF_FIFOn[COEFF_DATA]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * while the respective context RUN_EN bit is set to 0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) EASRC_CC_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(dev, "ST1 taps [%d] mus be lower than %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) goto ctx_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Update ctx ST1_NUM_TAPS in Context Control Extended 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) EASRC_CCE2_ST1_TAPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Prefilter Coefficient Write Select to write in ST1 coeff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) EASRC_CCE1_COEF_WS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ctx_priv->st1_coeff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ctx_priv->st1_num_taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ctx_priv->st1_addexp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto ctx_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ctx_priv->st2_num_taps > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_err(dev, "ST2 taps [%d] mus be lower than %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) goto ctx_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) EASRC_CCE1_PF_TSEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) EASRC_CCE1_PF_TSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Enable prefilter stage1 writeback floating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * which is used for FLOAT_LE case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) EASRC_CCE1_PF_ST1_WBFP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) EASRC_CCE1_PF_ST1_WBFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) EASRC_CCE1_PF_EXP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Update ctx ST2_NUM_TAPS in Context Control Extended 2 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) EASRC_CCE2_ST2_TAPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Prefilter Coefficient Write Select to write in ST2 coeff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) EASRC_CCE1_COEF_WS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ctx_priv->st2_coeff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ctx_priv->st2_num_taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ctx_priv->st2_addexp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto ctx_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ctx_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct fsl_easrc_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int st1_mem_alloc = 0, st2_mem_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int pf_mem_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int max_channels = 8 - slot->num_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ctx_priv->st1_num_taps > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ctx_priv->st2_num_taps > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) st1_mem_alloc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) st1_mem_alloc = ctx_priv->st1_num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ctx_priv->st2_num_taps > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) st2_mem_alloc = ctx_priv->st2_num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pf_mem_alloc = st1_mem_alloc + st2_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (pf_mem_alloc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) channels = (6144 - slot->pf_mem_used) / pf_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) channels = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (channels < max_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) max_channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return max_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct fsl_easrc_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned int slot_ctx_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned int *req_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned int *start_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned int *avail_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned int reg0, reg1, reg2, reg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (slot->slot_index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (*req_channels <= *avail_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) slot->num_channel = *req_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) *req_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) slot->num_channel = *avail_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *req_channels -= *avail_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) slot->min_channel = *start_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) slot->max_channel = *start_channel + slot->num_channel - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) slot->ctx_index = ctx->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) slot->busy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *start_channel += slot->num_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) regmap_update_bits(easrc->regmap, reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) EASRC_DPCS0R0_MAXCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) EASRC_DPCS0R0_MAXCH(slot->max_channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) regmap_update_bits(easrc->regmap, reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) EASRC_DPCS0R0_MINCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) EASRC_DPCS0R0_MINCH(slot->min_channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) regmap_update_bits(easrc->regmap, reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) EASRC_DPCS0R0_NUMCH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) EASRC_DPCS0R0_NUMCH(slot->num_channel - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) regmap_update_bits(easrc->regmap, reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) EASRC_DPCS0R0_CTXNUM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) EASRC_DPCS0R0_CTXNUM(slot->ctx_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ctx_priv->st1_num_taps > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ctx_priv->st2_num_taps > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) st1_mem_alloc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) (ctx_priv->st1_num_taps - 1) * slot->num_channel *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ctx_priv->st1_num_exp + slot->num_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) slot->pf_mem_used = st1_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) regmap_update_bits(easrc->regmap, reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) EASRC_DPCS0R2_ST1_MA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) EASRC_DPCS0R2_ST1_MA(st1_mem_alloc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (slot->slot_index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) addr = PREFILTER_MEM_LEN - st1_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) regmap_update_bits(easrc->regmap, reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) EASRC_DPCS0R2_ST1_SA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) EASRC_DPCS0R2_ST1_SA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ctx_priv->st2_num_taps > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) regmap_update_bits(easrc->regmap, reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) EASRC_DPCS0R1_ST1_EXP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) EASRC_DPCS0R1_ST1_EXP(st1_chanxexp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) slot->pf_mem_used += st2_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) regmap_update_bits(easrc->regmap, reg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) EASRC_DPCS0R3_ST2_MA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) EASRC_DPCS0R3_ST2_MA(st2_mem_alloc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (slot->slot_index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) addr = st1_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) regmap_update_bits(easrc->regmap, reg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) EASRC_DPCS0R3_ST2_SA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) EASRC_DPCS0R3_ST2_SA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) regmap_update_bits(easrc->regmap, reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * fsl_easrc_config_slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * A single context can be split amongst any of the 4 context processing pipes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * in the design.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * The total number of channels consumed within the context processor must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * less than or equal to 8. if a single context is configured to contain more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * than 8 channels then it must be distributed across multiple context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * processing pipe slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int req_channels = ctx->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int start_channel = 0, avail_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct fsl_easrc_slot *slot0, *slot1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct fsl_easrc_slot *slota, *slotb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (req_channels <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) slot0 = &easrc_priv->slot[i][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) slot1 = &easrc_priv->slot[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (slot0->busy && slot1->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else if ((slot0->busy && slot0->ctx_index == ctx->index) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) (slot1->busy && slot1->ctx_index == ctx->index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) } else if (!slot0->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) slota = slot0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) slotb = slot1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) slota->slot_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) } else if (!slot1->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) slota = slot1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) slotb = slot0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) slota->slot_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!slota || !slotb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (avail_channel <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &start_channel, &avail_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (req_channels > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (req_channels > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(&easrc->pdev->dev, "no avail slot.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * fsl_easrc_release_slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Clear the slot configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (easrc_priv->slot[i][0].busy &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) easrc_priv->slot[i][0].ctx_index == ctx->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) easrc_priv->slot[i][0].busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) easrc_priv->slot[i][0].num_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) easrc_priv->slot[i][0].pf_mem_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* set registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (easrc_priv->slot[i][1].busy &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) easrc_priv->slot[i][1].ctx_index == ctx->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) easrc_priv->slot[i][1].busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) easrc_priv->slot[i][1].num_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) easrc_priv->slot[i][1].pf_mem_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* set registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * fsl_easrc_config_context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * Configure the register relate with context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct fsl_easrc_ctx_priv *ctx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct fsl_asrc_pair *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (ctx_id >= EASRC_CTX_MAX_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(dev, "Invalid context id[%d]\n", ctx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ctx = easrc->pair[ctx_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) fsl_easrc_normalize_rates(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = fsl_easrc_set_rs_ratio(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Initialize the context coeficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = fsl_easrc_prefilter_config(easrc, ctx->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) spin_lock_irqsave(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = fsl_easrc_config_slot(easrc, ctx->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) spin_unlock_irqrestore(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * Both prefilter and resampling filters can use following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * initialization modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * 2 - zero-fil mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * 1 - replication mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * 0 - software control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) EASRC_CCE1_RS_INIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) EASRC_CCE1_PF_INIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * Context Input FIFO Watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * DMA request is generated when input FIFO < FIFO_WTMK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) EASRC_CC_FIFO_WTMK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * Context Output FIFO Watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * DMA request is generated when output FIFO > FIFO_WTMK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * So we set fifo_wtmk -1 to register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) EASRC_COC_FIFO_WTMK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Number of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) EASRC_CC_CHEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) EASRC_CC_CHEN(ctx->channels - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct fsl_easrc_data_fmt *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) snd_pcm_format_t raw_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Context Input Floating Point Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * 0 - Integer Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * 1 - Single Precision FP Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) fmt->floating_point = !snd_pcm_format_linear(raw_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) fmt->sample_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) fmt->iec958 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Get the data width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) switch (snd_pcm_format_width(raw_fmt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) fmt->width = EASRC_WIDTH_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) fmt->addexp = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) fmt->width = EASRC_WIDTH_20_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) fmt->addexp = 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) fmt->width = EASRC_WIDTH_24_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) fmt->addexp = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fmt->width = EASRC_WIDTH_32_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) fmt->addexp = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) switch (raw_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) fmt->width = easrc_priv->bps_iec958[ctx->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) fmt->iec958 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) fmt->floating_point = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (fmt->width == EASRC_WIDTH_16_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) fmt->sample_pos = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) fmt->addexp = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) } else if (fmt->width == EASRC_WIDTH_20_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) fmt->sample_pos = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fmt->addexp = 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) } else if (fmt->width == EASRC_WIDTH_24_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) fmt->sample_pos = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) fmt->addexp = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * Data Endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * 0 - Little-Endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * 1 - Big-Endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = snd_pcm_format_big_endian(raw_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) fmt->endianness = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Input Data sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * 0b - Signed Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * 1b - Unsigned Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) snd_pcm_format_t *in_raw_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) snd_pcm_format_t *out_raw_format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Get the bitfield values for input data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (in_raw_format && out_raw_format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) EASRC_CC_BPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) EASRC_CC_BPS(in_fmt->width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) EASRC_CC_ENDIANNESS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) EASRC_CC_FMT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) in_fmt->floating_point << EASRC_CC_FMT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) EASRC_CC_INSIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) in_fmt->unsign << EASRC_CC_INSIGN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* In Sample Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) EASRC_CC_SAMPLE_POS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) EASRC_CC_SAMPLE_POS(in_fmt->sample_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Get the bitfield values for input data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (in_raw_format && out_raw_format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) EASRC_COC_BPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) EASRC_COC_BPS(out_fmt->width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) EASRC_COC_ENDIANNESS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) EASRC_COC_FMT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) out_fmt->floating_point << EASRC_COC_FMT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) EASRC_COC_OUTSIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Out Sample Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) EASRC_COC_SAMPLE_POS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) EASRC_COC_SAMPLE_POS(out_fmt->sample_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) EASRC_COC_IEC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * The ASRC provides interleaving support in hardware to ensure that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * variety of sample sources can be internally combined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * to conform with this format. Interleaving parameters are accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * through the ASRC_CTRL_IN_ACCESSa and ASRC_CTRL_OUT_ACCESSa registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct fsl_easrc_ctx_priv *ctx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct fsl_asrc *easrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* input interleaving parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) EASRC_CIA_ITER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) EASRC_CIA_ITER(ctx_priv->in_params.iterations));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) EASRC_CIA_GRLEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) EASRC_CIA_GRLEN(ctx_priv->in_params.group_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) EASRC_CIA_ACCLEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* output interleaving parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) EASRC_COA_ITER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) EASRC_COA_ITER(ctx_priv->out_params.iterations));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) EASRC_COA_GRLEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) EASRC_COA_GRLEN(ctx_priv->out_params.group_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) EASRC_COA_ACCLEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) EASRC_COA_ACCLEN(ctx_priv->out_params.access_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * Request one of the available contexts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * Returns a negative number on error and >=0 as context id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) enum asrc_pair_index index = ASRC_INVALID_PAIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) spin_lock_irqsave(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (easrc->pair[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (index == ASRC_INVALID_PAIR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(dev, "all contexts are busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) } else if (channels > easrc->channel_avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(dev, "can't give the required channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ctx->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ctx->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) easrc->pair[index] = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) easrc->channel_avail -= channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) spin_unlock_irqrestore(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * Release the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * This funciton is mainly doing the revert thing in request context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static void fsl_easrc_release_context(struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct fsl_asrc *easrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) spin_lock_irqsave(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) fsl_easrc_release_slot(easrc, ctx->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) easrc->channel_avail += ctx->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) easrc->pair[ctx->index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) spin_unlock_irqrestore(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * Start the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * Enable the DMA request and context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int fsl_easrc_start_context(struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) EASRC_CC_EN_MASK, EASRC_CC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * Stop the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * Disable the DMA request and context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) int val, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) int size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) int retry = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (val & EASRC_CC_EN_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) regmap_update_bits(easrc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) EASRC_CC_STOP_MASK, EASRC_CC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) val &= EASRC_SFS_NSGO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) size = val >> EASRC_SFS_NSGO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* Read FIFO, drop the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) for (i = 0; i < size * ctx->channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* Check RUN_STOP_DONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (val & EASRC_IRQF_RSD(1 << ctx->index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*Clear RUN_STOP_DONE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) regmap_write_bits(easrc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) REG_EASRC_IRQF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) EASRC_IRQF_RSD(1 << ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) EASRC_IRQF_RSD(1 << ctx->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) } while (--retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (retry == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_warn(&easrc->pdev->dev, "RUN STOP fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) EASRC_CC_FWMDE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) EASRC_COC_FWMDE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) bool dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct fsl_asrc *easrc = ctx->asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) enum asrc_pair_index index = ctx->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* Example of dma name: ctx0_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return dma_request_slave_channel(&easrc->pdev->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const unsigned int easrc_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) 8000, 11025, 12000, 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) 22050, 24000, 32000, 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) 48000, 64000, 88200, 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) 128000, 176400, 192000, 256000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) 352800, 384000, 705600, 768000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .count = ARRAY_SIZE(easrc_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .list = easrc_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int fsl_easrc_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) &easrc_rate_constraints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static int fsl_easrc_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct fsl_asrc_pair *ctx = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ret = fsl_easrc_start_context(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret = fsl_easrc_stop_context(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int fsl_easrc_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct device *dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct fsl_asrc_pair *ctx = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) snd_pcm_format_t format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ret = fsl_easrc_request_context(channels, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dev_err(dev, "failed to request context\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ctx_priv->ctx_streams |= BIT(substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * Set the input and output ratio so we can compute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * the resampling ratio in RS_LOW/HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ctx_priv->in_params.sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ctx_priv->in_params.sample_format = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ctx_priv->out_params.sample_rate = easrc->asrc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ctx_priv->out_params.sample_format = easrc->asrc_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ctx_priv->out_params.sample_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ctx_priv->out_params.sample_format = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ctx_priv->in_params.sample_rate = easrc->asrc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ctx_priv->in_params.sample_format = easrc->asrc_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ctx->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ctx_priv->in_params.fifo_wtmk = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ctx_priv->out_params.fifo_wtmk = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * Do only rate conversion and keep the same format for input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * and output data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret = fsl_easrc_set_ctx_format(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) &ctx_priv->in_params.sample_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) &ctx_priv->out_params.sample_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) dev_err(dev, "failed to set format %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ret = fsl_easrc_config_context(easrc, ctx->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_err(dev, "failed to config context\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ctx_priv->in_params.iterations = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ctx_priv->in_params.group_len = ctx->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ctx_priv->in_params.access_len = ctx->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ctx_priv->out_params.iterations = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ctx_priv->out_params.group_len = ctx->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ctx_priv->out_params.access_len = ctx->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ret = fsl_easrc_set_ctx_organziation(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) dev_err(dev, "failed to set fifo organization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static int fsl_easrc_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct fsl_asrc_pair *ctx = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct fsl_easrc_ctx_priv *ctx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (ctx_priv->ctx_streams & BIT(substream->stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ctx_priv->ctx_streams &= ~BIT(substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) fsl_easrc_release_context(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static struct snd_soc_dai_ops fsl_easrc_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .startup = fsl_easrc_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .trigger = fsl_easrc_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .hw_params = fsl_easrc_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .hw_free = fsl_easrc_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int fsl_easrc_dai_probe(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) snd_soc_dai_init_dma_data(cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) &easrc->dma_params_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) &easrc->dma_params_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static struct snd_soc_dai_driver fsl_easrc_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .probe = fsl_easrc_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .stream_name = "ASRC-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .rate_max = 768000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .formats = FSL_EASRC_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .stream_name = "ASRC-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .rate_max = 768000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .formats = FSL_EASRC_FORMATS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .ops = &fsl_easrc_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static const struct snd_soc_component_driver fsl_easrc_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .name = "fsl-easrc-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .controls = fsl_easrc_snd_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .num_controls = ARRAY_SIZE(fsl_easrc_snd_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static const struct reg_default fsl_easrc_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {REG_EASRC_WRFIFO(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {REG_EASRC_WRFIFO(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {REG_EASRC_WRFIFO(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {REG_EASRC_WRFIFO(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {REG_EASRC_RDFIFO(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {REG_EASRC_RDFIFO(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {REG_EASRC_RDFIFO(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {REG_EASRC_RDFIFO(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {REG_EASRC_CC(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {REG_EASRC_CC(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {REG_EASRC_CC(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {REG_EASRC_CC(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {REG_EASRC_CCE1(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {REG_EASRC_CCE1(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {REG_EASRC_CCE1(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {REG_EASRC_CCE1(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {REG_EASRC_CCE2(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {REG_EASRC_CCE2(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {REG_EASRC_CCE2(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {REG_EASRC_CCE2(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {REG_EASRC_CIA(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {REG_EASRC_CIA(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {REG_EASRC_CIA(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {REG_EASRC_CIA(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {REG_EASRC_DPCS0R0(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {REG_EASRC_DPCS0R0(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {REG_EASRC_DPCS0R0(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {REG_EASRC_DPCS0R0(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {REG_EASRC_DPCS0R1(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {REG_EASRC_DPCS0R1(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {REG_EASRC_DPCS0R1(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {REG_EASRC_DPCS0R1(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {REG_EASRC_DPCS0R2(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {REG_EASRC_DPCS0R2(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {REG_EASRC_DPCS0R2(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {REG_EASRC_DPCS0R2(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {REG_EASRC_DPCS0R3(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {REG_EASRC_DPCS0R3(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {REG_EASRC_DPCS0R3(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {REG_EASRC_DPCS0R3(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {REG_EASRC_DPCS1R0(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {REG_EASRC_DPCS1R0(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {REG_EASRC_DPCS1R0(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {REG_EASRC_DPCS1R0(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {REG_EASRC_DPCS1R1(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) {REG_EASRC_DPCS1R1(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {REG_EASRC_DPCS1R1(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {REG_EASRC_DPCS1R1(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {REG_EASRC_DPCS1R2(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {REG_EASRC_DPCS1R2(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {REG_EASRC_DPCS1R2(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {REG_EASRC_DPCS1R2(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {REG_EASRC_DPCS1R3(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {REG_EASRC_DPCS1R3(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {REG_EASRC_DPCS1R3(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {REG_EASRC_DPCS1R3(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {REG_EASRC_COC(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) {REG_EASRC_COC(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {REG_EASRC_COC(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {REG_EASRC_COC(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {REG_EASRC_COA(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {REG_EASRC_COA(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {REG_EASRC_COA(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {REG_EASRC_COA(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) {REG_EASRC_SFS(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {REG_EASRC_SFS(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {REG_EASRC_SFS(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {REG_EASRC_SFS(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {REG_EASRC_RRL(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {REG_EASRC_RRL(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {REG_EASRC_RRL(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {REG_EASRC_RRL(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {REG_EASRC_RRH(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {REG_EASRC_RRH(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {REG_EASRC_RRH(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) {REG_EASRC_RRH(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {REG_EASRC_RUC(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {REG_EASRC_RUC(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {REG_EASRC_RUC(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {REG_EASRC_RUC(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {REG_EASRC_RUR(0), 0x7FFFFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {REG_EASRC_RUR(1), 0x7FFFFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {REG_EASRC_RUR(2), 0x7FFFFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) {REG_EASRC_RUR(3), 0x7FFFFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {REG_EASRC_RCTCL, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {REG_EASRC_RCTCH, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {REG_EASRC_PCF(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {REG_EASRC_PCF(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) {REG_EASRC_PCF(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {REG_EASRC_PCF(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {REG_EASRC_CRCM, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {REG_EASRC_CRCC, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {REG_EASRC_IRQC, 0x00000FFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {REG_EASRC_IRQF, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {REG_EASRC_CS0(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {REG_EASRC_CS0(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {REG_EASRC_CS0(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {REG_EASRC_CS0(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {REG_EASRC_CS1(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {REG_EASRC_CS1(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {REG_EASRC_CS1(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {REG_EASRC_CS1(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {REG_EASRC_CS2(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {REG_EASRC_CS2(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {REG_EASRC_CS2(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {REG_EASRC_CS2(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {REG_EASRC_CS3(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {REG_EASRC_CS3(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {REG_EASRC_CS3(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {REG_EASRC_CS3(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {REG_EASRC_CS4(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {REG_EASRC_CS4(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {REG_EASRC_CS4(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {REG_EASRC_CS4(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {REG_EASRC_CS5(0), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {REG_EASRC_CS5(1), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {REG_EASRC_CS5(2), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {REG_EASRC_CS5(3), 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {REG_EASRC_DBGC, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {REG_EASRC_DBGS, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const struct regmap_range fsl_easrc_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static const struct regmap_access_table fsl_easrc_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .yes_ranges = fsl_easrc_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const struct regmap_range fsl_easrc_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const struct regmap_access_table fsl_easrc_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .yes_ranges = fsl_easrc_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static const struct regmap_range fsl_easrc_volatileable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const struct regmap_access_table fsl_easrc_volatileable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .yes_ranges = fsl_easrc_volatileable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static const struct regmap_config fsl_easrc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .max_register = REG_EASRC_DBGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .reg_defaults = fsl_easrc_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .rd_table = &fsl_easrc_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .wr_table = &fsl_easrc_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .volatile_table = &fsl_easrc_volatileable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct interp_params *interp = easrc_priv->interp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct prefil_params *prefil = easrc_priv->prefil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) struct device *dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (firm->magic != FIRMWARE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) dev_err(dev, "Wrong magic. Something went wrong!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev_dbg(dev, "\nInterpolation scenarios:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) for (i = 0; i < firm->interp_scen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (interp[i].magic != FIRMWARE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) dev_dbg(dev, "%d. wrong interp magic: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) i, interp[i].magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) interp[i].num_taps, interp[i].num_phases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) interp[i].center_tap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) for (i = 0; i < firm->prefil_scen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (prefil[i].magic != FIRMWARE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) dev_dbg(dev, "%d. wrong prefil magic: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) i, prefil[i].magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) prefil[i].insr, prefil[i].outsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) prefil[i].st1_taps, prefil[i].st2_taps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) dev_dbg(dev, "end of firmware dump\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static int fsl_easrc_get_firmware(struct fsl_asrc *easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct fsl_easrc_priv *easrc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) const struct firmware **fw_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) u32 pnum, inum, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) const u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) fw_p = &easrc_priv->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) data = easrc_priv->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) pnum = easrc_priv->firmware_hdr->prefil_scen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) inum = easrc_priv->firmware_hdr->interp_scen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (inum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) offset = sizeof(struct asrc_firmware_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) easrc_priv->interp = (struct interp_params *)(data + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (pnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) offset = sizeof(struct asrc_firmware_hdr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) inum * sizeof(struct interp_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) easrc_priv->prefil = (struct prefil_params *)(data + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) fsl_easrc_dump_firmware(easrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static irqreturn_t fsl_easrc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct device *dev = &easrc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (val & EASRC_IRQF_OER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) dev_dbg(dev, "output FIFO underflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (val & EASRC_IRQF_IFO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) dev_dbg(dev, "input FIFO overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return REG_EASRC_FIFO(dir, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const struct of_device_id fsl_easrc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) { .compatible = "fsl,imx8mn-easrc",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static int fsl_easrc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct fsl_easrc_priv *easrc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct fsl_asrc *easrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (!easrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (!easrc_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) easrc->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) easrc->private = easrc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (IS_ERR(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) dev_err(&pdev->dev, "failed ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) easrc->paddr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) easrc->regmap = devm_regmap_init_mmio_clk(dev, "mem", regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) &fsl_easrc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (IS_ERR(easrc->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) dev_err(dev, "failed to init regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) return PTR_ERR(easrc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) dev_err(dev, "no irq for node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dev_name(dev), easrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) dev_err(dev, "failed to claim irq %u: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) easrc->mem_clk = devm_clk_get(dev, "mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (IS_ERR(easrc->mem_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) dev_err(dev, "failed to get mem clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return PTR_ERR(easrc->mem_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* Set default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) easrc->channel_avail = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) easrc->get_dma_channel = fsl_easrc_get_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) easrc->request_pair = fsl_easrc_request_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) easrc->release_pair = fsl_easrc_release_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) easrc->get_fifo_addr = fsl_easrc_get_fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) easrc_priv->rs_num_taps = EASRC_RS_32_TAPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) easrc_priv->const_coeff = 0x3FF0000000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) dev_err(dev, "failed to asrc rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ret = of_property_read_u32(np, "fsl,asrc-format", &easrc->asrc_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) dev_err(dev, "failed to asrc format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (!(FSL_EASRC_FORMATS & (1ULL << easrc->asrc_format))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) dev_warn(dev, "unsupported format, switching to S24_LE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ret = of_property_read_string(np, "firmware-name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) &easrc_priv->fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev_err(dev, "failed to get firmware name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) platform_set_drvdata(pdev, easrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) spin_lock_init(&easrc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) regcache_cache_only(easrc->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ret = devm_snd_soc_register_component(dev, &fsl_easrc_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) &fsl_easrc_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dev_err(dev, "failed to register ASoC DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ret = devm_snd_soc_register_component(dev, &fsl_asrc_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) dev_err(&pdev->dev, "failed to register ASoC platform\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static int fsl_easrc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static __maybe_unused int fsl_easrc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct fsl_asrc *easrc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) regcache_cache_only(easrc->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) clk_disable_unprepare(easrc->mem_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) spin_lock_irqsave(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) easrc_priv->firmware_loaded = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) spin_unlock_irqrestore(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static __maybe_unused int fsl_easrc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) struct fsl_asrc *easrc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) struct fsl_easrc_priv *easrc_priv = easrc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) struct fsl_easrc_ctx_priv *ctx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct fsl_asrc_pair *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ret = clk_prepare_enable(easrc->mem_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) regcache_cache_only(easrc->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) regcache_mark_dirty(easrc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) regcache_sync(easrc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) spin_lock_irqsave(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (easrc_priv->firmware_loaded) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) spin_unlock_irqrestore(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) goto skip_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) easrc_priv->firmware_loaded = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) spin_unlock_irqrestore(&easrc->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ret = fsl_easrc_get_firmware(easrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) dev_err(dev, "failed to get firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) goto disable_mem_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) * Write Resampling Coefficients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) * The coefficient RAM must be configured prior to beginning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * any context processing within the ASRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ret = fsl_easrc_resampler_config(easrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dev_err(dev, "resampler config failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) goto disable_mem_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ctx = easrc->pair[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ctx_priv = ctx->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) fsl_easrc_set_rs_ratio(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ctx_priv->out_missed_sample = ctx_priv->in_filled_sample *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ctx_priv->out_params.sample_rate /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ctx_priv->in_params.sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) % ctx_priv->in_params.sample_rate != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ctx_priv->out_missed_sample += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ctx_priv->st1_coeff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ctx_priv->st1_num_taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ctx_priv->st1_addexp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) goto disable_mem_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ctx_priv->st2_coeff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ctx_priv->st2_num_taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) ctx_priv->st2_addexp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) goto disable_mem_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) skip_load:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) disable_mem_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) clk_disable_unprepare(easrc->mem_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static const struct dev_pm_ops fsl_easrc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) SET_RUNTIME_PM_OPS(fsl_easrc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) fsl_easrc_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static struct platform_driver fsl_easrc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .probe = fsl_easrc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .remove = fsl_easrc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .name = "fsl-easrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .pm = &fsl_easrc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .of_match_table = fsl_easrc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) module_platform_driver(fsl_easrc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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