^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _MPC8610_PCM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _MPC8610_PCM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) struct ccsr_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) u8 res0[0x100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct ccsr_dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) __be32 mr; /* Mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) __be32 sr; /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) __be32 eclndar; /* Current link descriptor extended addr reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) __be32 clndar; /* Current link descriptor address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __be32 satr; /* Source attributes register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) __be32 sar; /* Source address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __be32 datr; /* Destination attributes register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) __be32 dar; /* Destination address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __be32 bcr; /* Byte count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) __be32 enlndar; /* Next link descriptor extended address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) __be32 nlndar; /* Next link descriptor address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 res1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __be32 eclsdar; /* Current list descriptor extended addr reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __be32 clsdar; /* Current list descriptor address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __be32 enlsdar; /* Next list descriptor extended address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __be32 nlsdar; /* Next list descriptor address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __be32 ssr; /* Source stride register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __be32 dsr; /* Destination stride register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 res2[0x38];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) } channel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __be32 dgsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCSR_DMA_MR_BWC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CCSR_DMA_MR_BWC_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CCSR_DMA_MR_BWC(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCSR_DMA_MR_EMP_EN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCSR_DMA_MR_EMS_EN 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCSR_DMA_MR_DAHTS_1 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCSR_DMA_MR_DAHTS_2 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCSR_DMA_MR_DAHTS_4 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCSR_DMA_MR_DAHTS_8 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCSR_DMA_MR_SAHTS_MASK 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCSR_DMA_MR_SAHTS_1 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCSR_DMA_MR_SAHTS_2 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCSR_DMA_MR_SAHTS_4 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CCSR_DMA_MR_SAHTS_8 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCSR_DMA_MR_DAHE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CCSR_DMA_MR_SAHE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CCSR_DMA_MR_SRW 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CCSR_DMA_MR_EOSIE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CCSR_DMA_MR_EOLNIE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CCSR_DMA_MR_EOLSIE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CCSR_DMA_MR_EIE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CCSR_DMA_MR_XFE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CCSR_DMA_MR_CDSM_SWSM 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CCSR_DMA_MR_CA 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CCSR_DMA_MR_CTM 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CCSR_DMA_MR_CC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CCSR_DMA_MR_CS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CCSR_DMA_SR_TE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CCSR_DMA_SR_CH 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CCSR_DMA_SR_PE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CCSR_DMA_SR_EOLNI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CCSR_DMA_SR_CB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CCSR_DMA_SR_EOSI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CCSR_DMA_SR_EOLSI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ECLNDAR takes bits 32-36 of the CLNDAR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return (x >> 32) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CCSR_DMA_CLNDAR_EOSIE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* SATR and DATR, combined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CCSR_DMA_ATR_PBATMU 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CCSR_DMA_ATR_TFLOWLVL_0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CCSR_DMA_ATR_TFLOWLVL_1 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CCSR_DMA_ATR_TFLOWLVL_2 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CCSR_DMA_ATR_TFLOWLVL_3 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CCSR_DMA_ATR_PCIORDER 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CCSR_DMA_ATR_SME 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CCSR_DMA_ATR_NOSNOOP 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CCSR_DMA_ATR_SNOOP 0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CCSR_DMA_ATR_ESAD_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * List Descriptor for extended chaining mode DMA operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * The CLSDAR register points to the first (in a linked-list) List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Descriptor. Each object must be aligned on a 32-byte boundary. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * list descriptor points to a linked-list of link Descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct fsl_dma_list_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __be64 next; /* Address of next list descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __be64 first_link; /* Address of first link descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __be32 source; /* Source stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __be32 dest; /* Destination stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 res[8]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } __attribute__ ((aligned(32), packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Link Descriptor for basic and extended chaining mode DMA operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * A Link Descriptor points to a single DMA buffer. Each link descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * must be aligned on a 32-byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct fsl_dma_link_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __be32 source_attr; /* Programmed into SATR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __be32 source_addr; /* Programmed into SAR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __be32 dest_attr; /* Programmed into DATR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __be32 dest_addr; /* Programmed into DAR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __be64 next; /* Address of next link descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __be32 count; /* Byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 res[4]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } __attribute__ ((aligned(32), packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags