^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale DMA ALSA SoC PCM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Timur Tabi <timur@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2007-2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // This driver implements ASoC support for the Elo DMA controller, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // the PCM driver is what handles the DMA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "fsl_dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_NAME "fsl_dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The formats that the DMA controller supports, which is anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * that is 8, 16, or 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SNDRV_PCM_FMTBIT_U8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SNDRV_PCM_FMTBIT_S16_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SNDRV_PCM_FMTBIT_U16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SNDRV_PCM_FMTBIT_U16_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SNDRV_PCM_FMTBIT_S24_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SNDRV_PCM_FMTBIT_U24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SNDRV_PCM_FMTBIT_U24_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SNDRV_PCM_FMTBIT_S32_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SNDRV_PCM_FMTBIT_S32_BE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SNDRV_PCM_FMTBIT_U32_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SNDRV_PCM_FMTBIT_U32_BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct dma_object {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct snd_soc_component_driver dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dma_addr_t ssi_stx_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dma_addr_t ssi_srx_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int ssi_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ccsr_dma_channel __iomem *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bool assigned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The number of DMA links to use. Two is the bare minimum, but if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * have really small links you might need more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NUM_DMA_LINKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /** fsl_dma_private: p-substream DMA data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Each substream has a 1-to-1 association with a DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * The link[] array is first because it needs to be aligned on a 32-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * boundary, so putting it first will ensure alignment without padding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @link[]: array of link descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @dma_channel: pointer to the DMA channel's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @irq: IRQ for this DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @substream: pointer to the substream object, needed by the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @ssi_sxx_phys: bus address of the STX or SRX register to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @ld_buf_phys: physical address of the LD buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @current_link: index into link[] of the link currently being processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @dma_buf_phys: physical address of the DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @dma_buf_next: physical address of the next period to process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @dma_buf_end: physical address of the byte after the end of the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @buffer period_size: the size of a single period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @num_periods: the number of periods in the DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct fsl_dma_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ccsr_dma_channel __iomem *dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dma_addr_t ssi_sxx_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int ssi_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_addr_t ld_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int current_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dma_addr_t dma_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dma_addr_t dma_buf_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dma_addr_t dma_buf_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) size_t period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * fsl_dma_hardare: define characteristics of the PCM hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * The PCM hardware is the Freescale DMA controller. This structure defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * the capabilities of that hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Since the sampling rate and data format are not controlled by the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * controller, we specify no limits for those values. The only exception is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * period_bytes_min, which is set to a reasonably low value to prevent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * DMA controller from generating too many interrupts per second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Since each link descriptor has a 32-bit byte count field, we set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * period_bytes_max to the largest 32-bit number. We also have no maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * number of periods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * limitation in the SSI driver requires the sample rates for playback and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * capture to be the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct snd_pcm_hardware fsl_dma_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SNDRV_PCM_INFO_JOINT_DUPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SNDRV_PCM_INFO_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .formats = FSLDMA_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .period_bytes_min = 512, /* A reasonable limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .period_bytes_max = (u32) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .periods_min = NUM_DMA_LINKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .periods_max = (unsigned int) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * This function should be called by the ISR whenever the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * halts data transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) snd_pcm_stop_xrun(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * fsl_dma_update_pointers - update LD pointers to point to the next period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * As each period is completed, this function changes the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * descriptor pointers for that period to point to the next period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct fsl_dma_link_descriptor *link =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &dma_private->link[dma_private->current_link];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Update our link descriptors to point to the next period. On a 36-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * system, we also need to update the ESAD bits. We also set (keep) the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * snoop bits. See the comments in fsl_dma_hw_params() about snooping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #ifdef CONFIG_PHYS_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) upper_32_bits(dma_private->dma_buf_next));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_PHYS_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) upper_32_bits(dma_private->dma_buf_next));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Update our variables for next time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dma_private->dma_buf_next += dma_private->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dma_private->dma_buf_next = dma_private->dma_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (++dma_private->current_link >= NUM_DMA_LINKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dma_private->current_link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * fsl_dma_isr: interrupt handler for the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @irq: IRQ of the DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @dev_id: pointer to the dma_private structure for this DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct fsl_dma_private *dma_private = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct snd_pcm_substream *substream = dma_private->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct device *dev = rtd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 sr, sr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* We got an interrupt, so read the status register to see what we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) were interrupted for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) sr = in_be32(&dma_channel->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (sr & CCSR_DMA_SR_TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(dev, "dma transmit error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) fsl_dma_abort_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sr2 |= CCSR_DMA_SR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (sr & CCSR_DMA_SR_CH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (sr & CCSR_DMA_SR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(dev, "dma programming error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) fsl_dma_abort_stream(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sr2 |= CCSR_DMA_SR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (sr & CCSR_DMA_SR_EOLNI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sr2 |= CCSR_DMA_SR_EOLNI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (sr & CCSR_DMA_SR_CB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (sr & CCSR_DMA_SR_EOSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Tell ALSA we completed a period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Update our link descriptors to point to the next period. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * only need to do this if the number of periods is not equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * the number of links.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (dma_private->num_periods != NUM_DMA_LINKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fsl_dma_update_pointers(dma_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) sr2 |= CCSR_DMA_SR_EOSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (sr & CCSR_DMA_SR_EOLSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sr2 |= CCSR_DMA_SR_EOLSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Clear the bits that we set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (sr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) out_be32(&dma_channel->sr, sr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * fsl_dma_new: initialize this PCM driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This function is called when the codec driver calls snd_soc_new_pcms(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * once for each .dai_link in the machine driver's snd_soc_card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * is specified. Therefore, any DMA buffers we allocate will always be in low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * memory, but we support for 36-bit physical addresses anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Regardless of where the memory is actually allocated, since the device can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int fsl_dma_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Some codecs have separate DAIs for playback and capture, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * should allocate a DMA buffer only for the streams that are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) fsl_dma_hardware.buffer_bytes_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(card->dev, "can't alloc playback dma buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) fsl_dma_hardware.buffer_bytes_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(card->dev, "can't alloc capture dma buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * fsl_dma_open: open a new substream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Each substream has its own DMA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * descriptors that ping-pong from one period to the next. For example, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * there are six periods and two link descriptors, this is how they look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * before playback starts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * The last link descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * ____________ points back to the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * V |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * ___ ___ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * | |->| |->|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * |___| |___|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * V V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * _________________________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * | | | | | | | The DMA buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * | | | | | | | divided into 6 parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * |______|______|______|______|______|______|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * and here's how they look after the first period is finished playing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * ____________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * V |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * ___ ___ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * | |->| |->|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * |___| |___|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * |______________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * V V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * _________________________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * |______|______|______|______|______|______|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * The first link descriptor now points to the third period. The DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * controller is currently playing the second period. When it finishes, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * will jump back to the first descriptor and play the third period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * There are four reasons we do this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * 1. The only way to get the DMA controller to automatically restart the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * transfer when it gets to the end of the buffer is to use chaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * mode. Basic direct mode doesn't offer that feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * 2. We need to receive an interrupt at the end of every period. The DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * controller can generate an interrupt at the end of every link transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * (aka segment). Making each period into a DMA segment will give us the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * interrupts we need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * 3. By creating only two link descriptors, regardless of the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * periods, we do not need to reallocate the link descriptors if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * number of periods changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * 4. All of the audio data is still stored in a single, contiguous DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * buffer, which is what ALSA expects. We're just dividing it into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * contiguous parts, and creating a link descriptor for each one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int fsl_dma_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct device *dev = component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct dma_object *dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) container_of(component->driver, struct dma_object, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct fsl_dma_private *dma_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ccsr_dma_channel __iomem *dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dma_addr_t ld_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u64 temp_link; /* Pointer to next link descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Reject any DMA buffer whose size is not a multiple of the period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * size. We need to make sure that the DMA buffer can be evenly divided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * into periods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = snd_pcm_hw_constraint_integer(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(dev, "invalid buffer size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (dma->assigned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(dev, "dma channel already assigned\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &ld_buf_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!dma_private) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(dev, "can't allocate dma private data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_private->dma_channel = dma->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dma_private->irq = dma->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dma_private->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dma_private->ld_buf_phys = ld_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dma_private->dma_buf_phys = substream->dma_buffer.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dma_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_private->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dma_free_coherent(dev, sizeof(struct fsl_dma_private),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dma_private, dma_private->ld_buf_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dma->assigned = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) runtime->private_data = dma_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Program the fixed DMA controller parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dma_channel = dma_private->dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) temp_link = dma_private->ld_buf_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sizeof(struct fsl_dma_link_descriptor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) for (i = 0; i < NUM_DMA_LINKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dma_private->link[i].next = cpu_to_be64(temp_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) temp_link += sizeof(struct fsl_dma_link_descriptor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* The last link descriptor points to the first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Tell the DMA controller where the first link descriptor is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) out_be32(&dma_channel->clndar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) out_be32(&dma_channel->eclndar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* The manual says the BCR must be clear before enabling EMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) out_be32(&dma_channel->bcr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Program the mode register for interrupts, external master control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * and source/destination hold. Also clear the Channel Abort bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mr = in_be32(&dma_channel->mr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * We want External Master Start and External Master Pause enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * because the SSI is controlling the DMA controller. We want the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * controller to be set up in advance, and then we signal only the SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * to start transferring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * We want End-Of-Segment Interrupts enabled, because this will generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * an interrupt at the end of each segment (each link descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * represents one segment). Each DMA segment is the same thing as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * ALSA period, so this is how we get an interrupt at the end of every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * We want Error Interrupt enabled, so that we can get an error if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * the DMA controller is mis-programmed somehow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) CCSR_DMA_MR_EMS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* For playback, we want the destination address to be held. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) capture, set the source address to be held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) out_be32(&dma_channel->mr, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * fsl_dma_hw_params: continue initializing the DMA links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * This function obtains hardware parameters about the opened stream and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * programs the DMA controller accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * One drawback of big-endian is that when copying integers of different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * sizes to a fixed-sized register, the address to which the integer must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * copied is dependent on the size of the integer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * For example, if P is the address of a 32-bit register, and X is a 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * integer, then X should be copied to address P. However, if X is a 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * integer, then it should be copied to P+2. If X is an 8-bit register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * then it should be copied to P+3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * So for playback of 8-bit samples, the DMA controller must transfer single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * For 24-bit samples, the offset is 1 byte. However, the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * and 8 bytes at a time). So we do not support packed 24-bit samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * 24-bit data must be padded to 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int fsl_dma_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct fsl_dma_private *dma_private = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct device *dev = component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Number of bits per sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int sample_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) snd_pcm_format_physical_width(params_format(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Number of bytes per frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int sample_bytes = sample_bits / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Bus address of SSI STX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Size of the DMA buffer, in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) size_t buffer_size = params_buffer_bytes(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Number of bytes per period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) size_t period_size = params_period_bytes(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Pointer to next period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dma_addr_t temp_addr = substream->dma_buffer.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Pointer to DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 mr; /* DMA Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Initialize our DMA tracking variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dma_private->period_size = period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dma_private->num_periods = params_periods(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dma_private->dma_buf_next = dma_private->dma_buf_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (NUM_DMA_LINKS * period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* This happens if the number of periods == NUM_DMA_LINKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dma_private->dma_buf_next = dma_private->dma_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Due to a quirk of the SSI's STX register, the target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * for the DMA operations depends on the sample size. So we calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * that offset here. While we're at it, also tell the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * how much data to transfer per sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) switch (sample_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ssi_sxx_phys += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ssi_sxx_phys += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* We should never get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(dev, "unsupported sample size %u\n", sample_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * BWC determines how many bytes are sent/received before the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * controller checks the SSI to see if it needs to stop. BWC should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * always be a multiple of the frame size, so that we always transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * whole frames. Each frame occupies two slots in the FIFO. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * (MR[BWC] can only represent even powers of two).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * To simplify the process, we set BWC to the largest value that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * less than or equal to the FIFO watermark. For playback, this ensures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * that we transfer the maximum amount without overrunning the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * For capture, this ensures that we transfer the maximum amount without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * underrunning the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * f = SSI FIFO depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * w = SSI watermark value (which equals f - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * b = DMA bandwidth count (in bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * s = sample size (in bytes, which equals frame_size * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * For playback, we never transmit more than the transmit FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * watermark, otherwise we might write more data than the FIFO can hold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * The watermark is equal to the FIFO depth minus two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * For capture, two equations must hold:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * w > f - (b / s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * w >= b / s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * So, b > 2 * s, but b must also be <= s * w. To simplify, we set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * b = s * w, which is equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * (dma_private->ssi_fifo_depth - 2) * sample_bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) out_be32(&dma_channel->mr, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (i = 0; i < NUM_DMA_LINKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct fsl_dma_link_descriptor *link = &dma_private->link[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) link->count = cpu_to_be32(period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* The snoop bit tells the DMA controller whether it should tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * the ECM to snoop during a read or write to an address. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * audio, we use DMA to transfer data between memory and an I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * device (the SSI's STX0 or SRX0 register). Snooping is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * needed if there is a cache, so we need to snoop memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * addresses only. For playback, that means we snoop the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * but not the destination. For capture, we snoop the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * destination but not the source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Note that failing to snoop properly is unlikely to cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * cache incoherency if the period size is larger than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * size of L1 cache. This is because filling in one period will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * flush out the data for the previous period. So if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * increased period_bytes_min to a large enough size, you might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * get more performance by not snooping, and you'll still be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * okay. You'll need to update fsl_dma_update_pointers() also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) link->source_addr = cpu_to_be32(temp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) upper_32_bits(temp_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) link->dest_addr = cpu_to_be32(ssi_sxx_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) upper_32_bits(ssi_sxx_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) link->source_addr = cpu_to_be32(ssi_sxx_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) upper_32_bits(ssi_sxx_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) link->dest_addr = cpu_to_be32(temp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) upper_32_bits(temp_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) temp_addr += period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * fsl_dma_pointer: determine the current position of the DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * This function is called by ALSA when ALSA wants to know where in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * stream buffer the hardware currently is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * For playback, the SAR register contains the physical address of the most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * recent DMA transfer. For capture, the value is in the DAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * The base address of the buffer is stored in the source_addr field of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * first link descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct fsl_dma_private *dma_private = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct device *dev = component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dma_addr_t position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) snd_pcm_uframes_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Obtain the current DMA pointer, but don't read the ESAD bits if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * only have 32-bit DMA addresses. This function is typically called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * in interrupt context, so we need to optimize it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) position = in_be32(&dma_channel->sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #ifdef CONFIG_PHYS_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) position |= (u64)(in_be32(&dma_channel->satr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) CCSR_DMA_ATR_ESAD_MASK) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) position = in_be32(&dma_channel->dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #ifdef CONFIG_PHYS_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) position |= (u64)(in_be32(&dma_channel->datr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) CCSR_DMA_ATR_ESAD_MASK) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * When capture is started, the SSI immediately starts to fill its FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * This means that the DMA controller is not started until the FIFO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * full. However, ALSA calls this function before that happens, when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * MR.DAR is still zero. In this case, just return zero to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * that nothing has been received yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!position)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if ((position < dma_private->dma_buf_phys) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) (position > dma_private->dma_buf_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(dev, "dma pointer is out of range, halting stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return SNDRV_PCM_POS_XRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * If the current address is just past the end of the buffer, wrap it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * around.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (frames == runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) frames = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * Release the resources allocated in fsl_dma_hw_params() and de-program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * This function can be called multiple times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int fsl_dma_hw_free(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct fsl_dma_private *dma_private = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (dma_private) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct ccsr_dma_channel __iomem *dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dma_channel = dma_private->dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Stop the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) out_be32(&dma_channel->mr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Reset all the other registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) out_be32(&dma_channel->sr, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) out_be32(&dma_channel->clndar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) out_be32(&dma_channel->eclndar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) out_be32(&dma_channel->satr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) out_be32(&dma_channel->sar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) out_be32(&dma_channel->datr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) out_be32(&dma_channel->dar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) out_be32(&dma_channel->bcr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) out_be32(&dma_channel->nlndar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) out_be32(&dma_channel->enlndar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * fsl_dma_close: close the stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int fsl_dma_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct fsl_dma_private *dma_private = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct device *dev = component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct dma_object *dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) container_of(component->driver, struct dma_object, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (dma_private) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (dma_private->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) free_irq(dma_private->irq, dma_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Deallocate the fsl_dma_private structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dma_free_coherent(dev, sizeof(struct fsl_dma_private),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dma_private, dma_private->ld_buf_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) substream->runtime->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dma->assigned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Remove this PCM driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void fsl_dma_free_dma_buffers(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) substream = pcm->streams[i].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) snd_dma_free_pages(&substream->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) substream->dma_buffer.area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) substream->dma_buffer.addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * find_ssi_node -- returns the SSI node that points to its DMA channel node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * Although this DMA driver attempts to operate independently of the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * devices, it still needs to determine some information about the SSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * that it's working with. Unfortunately, the device tree does not contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * a pointer from the DMA channel node to the SSI node -- the pointer goes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * other way. So we need to scan the device tree for SSI nodes until we find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * the one that points to the given DMA channel node. It's ugly, but at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * it's contained in this one function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct device_node *ssi_np, *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Check each DMA phandle to see if it points to us. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * assume that device_node pointers are a valid comparison.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (np == dma_channel_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ssi_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (np == dma_channel_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ssi_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int fsl_soc_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct dma_object *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct device_node *ssi_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) const uint32_t *iprop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Find the SSI node that points to us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ssi_np = find_ssi_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!ssi_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_err(&pdev->dev, "cannot find parent SSI node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret = of_address_to_resource(ssi_np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_err(&pdev->dev, "could not determine resources for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ssi_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) of_node_put(ssi_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dma = kzalloc(sizeof(*dma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) of_node_put(ssi_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dma->dai.name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dma->dai.open = fsl_dma_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dma->dai.close = fsl_dma_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dma->dai.hw_params = fsl_dma_hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dma->dai.hw_free = fsl_dma_hw_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dma->dai.pointer = fsl_dma_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dma->dai.pcm_construct = fsl_dma_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dma->dai.pcm_destruct = fsl_dma_free_dma_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Store the SSI-specific information that we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dma->ssi_stx_phys = res.start + REG_SSI_STX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dma->ssi_srx_phys = res.start + REG_SSI_SRX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (iprop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dma->ssi_fifo_depth = be32_to_cpup(iprop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Older 8610 DTs didn't have the fifo-depth property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dma->ssi_fifo_depth = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) of_node_put(ssi_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_err(&pdev->dev, "could not register platform\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) kfree(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dma->channel = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dma->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_set_drvdata(&pdev->dev, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int fsl_soc_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct dma_object *dma = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) iounmap(dma->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) irq_dispose_mapping(dma->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) kfree(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct of_device_id fsl_soc_dma_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { .compatible = "fsl,ssi-dma-channel", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static struct platform_driver fsl_soc_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .name = "fsl-pcm-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .of_match_table = fsl_soc_dma_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .probe = fsl_soc_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .remove = fsl_soc_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) module_platform_driver(fsl_soc_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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