^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __FSL_AUDMIX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __FSL_AUDMIX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FSL_AUDMIX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* AUDMIX Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FSL_AUDMIX_CTR 0x200 /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FSL_AUDMIX_STR 0x204 /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSL_AUDMIX_ATIVAL1 0x22c /* Attenuation Initial Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSL_AUDMIX_ATSTPUP1 0x230 /* Attenuation step up factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FSL_AUDMIX_ATSTPDN1 0x234 /* Attenuation step down factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FSL_AUDMIX_ATSTPTGT1 0x238 /* Attenuation step target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FSL_AUDMIX_ATTNVAL1 0x23c /* Attenuation Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSL_AUDMIX_ATSTP1 0x240 /* Attenuation step number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* AUDMIX Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSL_AUDMIX_CTR_MIXCLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSL_AUDMIX_CTR_MIXCLK_MASK BIT(FSL_AUDMIX_CTR_MIXCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FSL_AUDMIX_CTR_MIXCLK(i) ((i) << FSL_AUDMIX_CTR_MIXCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FSL_AUDMIX_CTR_OUTSRC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FSL_AUDMIX_CTR_OUTSRC_MASK (0x3 << FSL_AUDMIX_CTR_OUTSRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FSL_AUDMIX_CTR_OUTSRC(i) (((i) << FSL_AUDMIX_CTR_OUTSRC_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) & FSL_AUDMIX_CTR_OUTSRC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSL_AUDMIX_CTR_OUTWIDTH_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSL_AUDMIX_CTR_OUTWIDTH_MASK (0x7 << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FSL_AUDMIX_CTR_OUTWIDTH(i) (((i) << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) & FSL_AUDMIX_CTR_OUTWIDTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FSL_AUDMIX_CTR_OUTCKPOL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FSL_AUDMIX_CTR_OUTCKPOL_MASK BIT(FSL_AUDMIX_CTR_OUTCKPOL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FSL_AUDMIX_CTR_OUTCKPOL(i) ((i) << FSL_AUDMIX_CTR_OUTCKPOL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FSL_AUDMIX_CTR_MASKRTDF_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FSL_AUDMIX_CTR_MASKRTDF_MASK BIT(FSL_AUDMIX_CTR_MASKRTDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FSL_AUDMIX_CTR_MASKRTDF(i) ((i) << FSL_AUDMIX_CTR_MASKRTDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FSL_AUDMIX_CTR_MASKCKDF_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FSL_AUDMIX_CTR_MASKCKDF_MASK BIT(FSL_AUDMIX_CTR_MASKCKDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FSL_AUDMIX_CTR_MASKCKDF(i) ((i) << FSL_AUDMIX_CTR_MASKCKDF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FSL_AUDMIX_CTR_SYNCMODE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FSL_AUDMIX_CTR_SYNCMODE_MASK BIT(FSL_AUDMIX_CTR_SYNCMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FSL_AUDMIX_CTR_SYNCMODE(i) ((i) << FSL_AUDMIX_CTR_SYNCMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FSL_AUDMIX_CTR_SYNCSRC_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FSL_AUDMIX_CTR_SYNCSRC_MASK BIT(FSL_AUDMIX_CTR_SYNCSRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FSL_AUDMIX_CTR_SYNCSRC(i) ((i) << FSL_AUDMIX_CTR_SYNCSRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* AUDMIX Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FSL_AUDMIX_STR_RATEDIFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FSL_AUDMIX_STR_CLKDIFF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FSL_AUDMIX_STR_MIXSTAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FSL_AUDMIX_STR_MIXSTAT_MASK (0x3 << FSL_AUDMIX_STR_MIXSTAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FSL_AUDMIX_STR_MIXSTAT(i) (((i) & FSL_AUDMIX_STR_MIXSTAT_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) >> FSL_AUDMIX_STR_MIXSTAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* AUDMIX Attenuation Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FSL_AUDMIX_ATCR_AT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FSL_AUDMIX_ATCR_AT_UPDN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FSL_AUDMIX_ATCR_ATSTPDFI_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (0xfff << FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* AUDMIX Attenuation Initial Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FSL_AUDMIX_ATIVAL_ATINVAL_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* AUDMIX Attenuation Step Up Factor Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FSL_AUDMIX_ATSTPUP_ATSTEPUP_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* AUDMIX Attenuation Step Down Factor Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FSL_AUDMIX_ATSTPDN_ATSTEPDN_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* AUDMIX Attenuation Step Target Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FSL_AUDMIX_ATSTPTGT_ATSTPTG_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* AUDMIX Attenuation Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FSL_AUDMIX_ATTNVAL_ATCURVAL_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* AUDMIX Attenuation Step Number Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FSL_AUDMIX_ATSTP_STPCTR_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FSL_AUDMIX_MAX_DAIS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct fsl_audmix {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk *ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spinlock_t lock; /* Protect tdms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 tdms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* __FSL_AUDMIX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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