^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "fsl_audmix.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SOC_ENUM_SINGLE_S(xreg, xshift, xtexts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) SOC_ENUM_SINGLE(xreg, xshift, ARRAY_SIZE(xtexts), xtexts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *tdm_sel[] = { "TDM1", "TDM2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *mode_sel[] = { "Disabled", "TDM1", "TDM2", "Mixed", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *width_sel[] = { "16b", "18b", "20b", "24b", "32b", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *endis_sel[] = { "Disabled", "Enabled", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *updn_sel[] = { "Downward", "Upward", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *mask_sel[] = { "Unmask", "Mask", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct soc_enum fsl_audmix_enum[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* FSL_AUDMIX_CTR enums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MIXCLK_SHIFT, tdm_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTSRC_SHIFT, mode_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTWIDTH_SHIFT, width_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKRTDF_SHIFT, mask_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKCKDF_SHIFT, mask_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCMODE_SHIFT, endis_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCSRC_SHIFT, tdm_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* FSL_AUDMIX_ATCR0 enums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 1, updn_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* FSL_AUDMIX_ATCR1 enums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 1, updn_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct fsl_audmix_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 tdms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) char msg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct fsl_audmix_state prms[4][4] = {{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* DIS->DIS, do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .tdms = 0, .clk = 0, .msg = "" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* DIS->TDM1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* DIS->TDM2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DIS->MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }, { /* TDM1->DIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* TDM1->TDM1, do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .tdms = 0, .clk = 0, .msg = "" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* TDM1->TDM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* TDM1->MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }, { /* TDM2->DIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* TDM2->TDM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .tdms = 3, .clk = 1, .msg = "TDM2->TDM1: Please start both TDMs!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* TDM2->TDM2, do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .tdms = 0, .clk = 0, .msg = "" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* TDM2->MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, { /* MIX->DIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .tdms = 3, .clk = 0, .msg = "MIX->DIS: Please start both TDMs!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* MIX->TDM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .tdms = 3, .clk = 1, .msg = "MIX->TDM1: Please start both TDMs!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* MIX->TDM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .tdms = 3, .clk = 2, .msg = "MIX->TDM2: Please start both TDMs!\n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* MIX->MIX, do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .tdms = 0, .clk = 0, .msg = "" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int fsl_audmix_state_trans(struct snd_soc_component *comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int *mask, unsigned int *ctr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct fsl_audmix_state prm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Enforce all required TDMs are started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if ((priv->tdms & prm.tdms) != prm.tdms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_dbg(comp->dev, "%s", prm.msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) switch (prm.clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Set mix clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (*ctr) |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int fsl_audmix_put_mix_clk_src(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int *item = ucontrol->value.enumerated.item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int reg_val, val, mix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Get current state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) >> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val = snd_soc_enum_item_to_val(e, item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Ensure the current selected mixer clock is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * for configuration propagation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!(priv->tdms & BIT(mix_clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(comp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "Started TDM%d needed for config propagation!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mix_clk + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!(priv->tdms & BIT(val))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(comp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "The selected clock source has no TDM%d enabled!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return snd_soc_put_enum_double(kcontrol, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int fsl_audmix_put_out_src(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int *item = ucontrol->value.enumerated.item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 out_src, mix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int reg_val, val, mask = 0, ctr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Get current state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* "From" state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) >> FSL_AUDMIX_CTR_OUTSRC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) >> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* "To" state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = snd_soc_enum_item_to_val(e, item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Check if state is changing ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (out_src == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Ensure the current selected mixer clock is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * for configuration propagation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!(priv->tdms & BIT(mix_clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(comp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "Started TDM%d needed for config propagation!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mix_clk + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Check state transition constraints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Complete transition to new state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mask |= FSL_AUDMIX_CTR_OUTSRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ctr |= FSL_AUDMIX_CTR_OUTSRC(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* FSL_AUDMIX_CTR controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = "Mixing Clock Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .info = snd_soc_info_enum_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .put = fsl_audmix_put_mix_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .private_value = (unsigned long)&fsl_audmix_enum[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "Output Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .info = snd_soc_info_enum_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .put = fsl_audmix_put_out_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .private_value = (unsigned long)&fsl_audmix_enum[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SOC_ENUM("Output Width", fsl_audmix_enum[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SOC_ENUM("Sync Mode Config", fsl_audmix_enum[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SOC_ENUM("Sync Mode Clk Source", fsl_audmix_enum[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* TDM1 Attenuation controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SOC_ENUM("TDM1 Attenuation", fsl_audmix_enum[7]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SOC_ENUM("TDM1 Attenuation Direction", fsl_audmix_enum[8]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SOC_SINGLE("TDM1 Attenuation Step Divider", FSL_AUDMIX_ATCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 2, 0x00fff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SOC_SINGLE("TDM1 Attenuation Initial Value", FSL_AUDMIX_ATIVAL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SOC_SINGLE("TDM1 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SOC_SINGLE("TDM1 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SOC_SINGLE("TDM1 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* TDM2 Attenuation controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SOC_ENUM("TDM2 Attenuation", fsl_audmix_enum[9]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SOC_ENUM("TDM2 Attenuation Direction", fsl_audmix_enum[10]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SOC_SINGLE("TDM2 Attenuation Step Divider", FSL_AUDMIX_ATCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 2, 0x00fff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SOC_SINGLE("TDM2 Attenuation Initial Value", FSL_AUDMIX_ATIVAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SOC_SINGLE("TDM2 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SOC_SINGLE("TDM2 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SOC_SINGLE("TDM2 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0, 0x3ffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int fsl_audmix_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct snd_soc_component *comp = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 mask = 0, ctr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* AUDMIX is working in DSP_A format only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* For playback the AUDMIX is slave, and for record is master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Output data will be written on positive edge of the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Output data will be written on negative edge of the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int fsl_audmix_dai_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct fsl_audmix *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Capture stream shall not be handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_lock_irqsave(&priv->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) priv->tdms |= BIT(dai->driver->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) spin_unlock_irqrestore(&priv->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&priv->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) priv->tdms &= ~BIT(dai->driver->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) spin_unlock_irqrestore(&priv->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct snd_soc_dai_ops fsl_audmix_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .set_fmt = fsl_audmix_dai_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .trigger = fsl_audmix_dai_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct snd_soc_dai_driver fsl_audmix_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "audmix-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .stream_name = "AUDMIX-Playback-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .formats = FSL_AUDMIX_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .stream_name = "AUDMIX-Capture-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .formats = FSL_AUDMIX_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .ops = &fsl_audmix_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "audmix-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .stream_name = "AUDMIX-Playback-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .formats = FSL_AUDMIX_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .stream_name = "AUDMIX-Capture-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .channels_min = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .formats = FSL_AUDMIX_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .ops = &fsl_audmix_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct snd_soc_component_driver fsl_audmix_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = "fsl-audmix-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .controls = fsl_audmix_snd_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .num_controls = ARRAY_SIZE(fsl_audmix_snd_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case FSL_AUDMIX_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case FSL_AUDMIX_STR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case FSL_AUDMIX_ATCR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case FSL_AUDMIX_ATIVAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case FSL_AUDMIX_ATSTPUP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case FSL_AUDMIX_ATSTPDN0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case FSL_AUDMIX_ATSTPTGT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case FSL_AUDMIX_ATTNVAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case FSL_AUDMIX_ATSTP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case FSL_AUDMIX_ATCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case FSL_AUDMIX_ATIVAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case FSL_AUDMIX_ATSTPUP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case FSL_AUDMIX_ATSTPDN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case FSL_AUDMIX_ATSTPTGT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case FSL_AUDMIX_ATTNVAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case FSL_AUDMIX_ATSTP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case FSL_AUDMIX_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case FSL_AUDMIX_ATCR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case FSL_AUDMIX_ATIVAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case FSL_AUDMIX_ATSTPUP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case FSL_AUDMIX_ATSTPDN0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case FSL_AUDMIX_ATSTPTGT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case FSL_AUDMIX_ATCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case FSL_AUDMIX_ATIVAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case FSL_AUDMIX_ATSTPUP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case FSL_AUDMIX_ATSTPDN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case FSL_AUDMIX_ATSTPTGT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct reg_default fsl_audmix_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { FSL_AUDMIX_CTR, 0x00060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { FSL_AUDMIX_STR, 0x00003 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { FSL_AUDMIX_ATCR0, 0x00000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { FSL_AUDMIX_ATIVAL0, 0x3FFFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { FSL_AUDMIX_ATSTPUP0, 0x2AAAA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { FSL_AUDMIX_ATSTPDN0, 0x30000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { FSL_AUDMIX_ATSTPTGT0, 0x00010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { FSL_AUDMIX_ATTNVAL0, 0x00000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { FSL_AUDMIX_ATSTP0, 0x00000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { FSL_AUDMIX_ATCR1, 0x00000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { FSL_AUDMIX_ATIVAL1, 0x3FFFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { FSL_AUDMIX_ATSTPUP1, 0x2AAAA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { FSL_AUDMIX_ATSTPDN1, 0x30000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { FSL_AUDMIX_ATSTPTGT1, 0x00010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { FSL_AUDMIX_ATTNVAL1, 0x00000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { FSL_AUDMIX_ATSTP1, 0x00000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct regmap_config fsl_audmix_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .max_register = FSL_AUDMIX_ATSTP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .reg_defaults = fsl_audmix_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .num_reg_defaults = ARRAY_SIZE(fsl_audmix_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .readable_reg = fsl_audmix_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .writeable_reg = fsl_audmix_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct of_device_id fsl_audmix_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .compatible = "fsl,imx8qm-audmix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .data = "imx-audmix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int fsl_audmix_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct fsl_audmix *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) const char *mdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) of_id = of_match_device(fsl_audmix_ids, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!of_id || !of_id->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mdrv = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Get the addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) priv->regmap = devm_regmap_init_mmio_clk(dev, "ipg", regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &fsl_audmix_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(dev, "failed to init regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) priv->ipg_clk = devm_clk_get(dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (IS_ERR(priv->ipg_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(dev, "failed to get ipg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return PTR_ERR(priv->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) fsl_audmix_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ARRAY_SIZE(fsl_audmix_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(dev, "failed to register ASoC DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto err_disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) priv->pdev = platform_device_register_data(dev, mdrv, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (IS_ERR(priv->pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = PTR_ERR(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(dev, "failed to register platform %s: %d\n", mdrv, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto err_disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err_disable_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int fsl_audmix_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct fsl_audmix *priv = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) platform_device_unregister(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int fsl_audmix_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct fsl_audmix *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = clk_prepare_enable(priv->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_err(dev, "Failed to enable IPG clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regcache_cache_only(priv->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) regcache_mark_dirty(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return regcache_sync(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int fsl_audmix_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct fsl_audmix *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) regcache_cache_only(priv->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) clk_disable_unprepare(priv->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct dev_pm_ops fsl_audmix_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SET_RUNTIME_PM_OPS(fsl_audmix_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fsl_audmix_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct platform_driver fsl_audmix_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .probe = fsl_audmix_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .remove = fsl_audmix_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .name = "fsl-audmix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .of_match_table = fsl_audmix_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .pm = &fsl_audmix_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) module_platform_driver(fsl_audmix_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MODULE_DESCRIPTION("NXP AUDMIX ASoC DAI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_ALIAS("platform:fsl-audmix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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