^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * fsl_asrc.h - Freescale ASRC ALSA SoC header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Nicolin Chen <nicoleotsuka@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _FSL_ASRC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _FSL_ASRC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "fsl_asrc_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ASRC_DMA_BUFFER_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ASRC_INPUTFIFO_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ASRC_OUTPUTFIFO_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASRC_FIFO_THRESHOLD_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ASRC_FIFO_THRESHOLD_MAX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ASRC_MAX_BUFFER_SIZE (1024 * 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ASRC_OUTPUT_LAST_SAMPLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IDEAL_RATIO_RATE 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_ASRCTR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_ASRIER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_ASRCNCR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_ASRCFG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_ASRCSR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_ASRCDR1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_ASRCDR2 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_ASRCDR(i) ((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_ASRSTR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_ASRRA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_ASRRB 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_ASRRC 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_ASRPM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_ASRPM2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_ASRPM3 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_ASRPM4 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_ASRPM5 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_ASRTFR1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_ASRCCR 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_ASRDIA 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_ASRDOA 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_ASRDIB 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_ASRDOB 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_ASRDIC 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_ASRDOC 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_ASRDI(i) (REG_ASRDIA + (i << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_ASRDO(i) (REG_ASRDOA + (i << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_ASRDx(x, i) ((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_ASRIDRHA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_ASRIDRLA 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_ASRIDRHB 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_ASRIDRLB 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_ASRIDRHC 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_ASRIDRLC 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_ASRIDRH(i) (REG_ASRIDRHA + (i << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_ASRIDRL(i) (REG_ASRIDRLA + (i << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_ASR76K 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_ASR56K 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_ASRMCRA 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_ASRFSTA 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_ASRMCRB 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_ASRFSTB 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_ASRMCRC 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_ASRFSTC 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_ASRMCR(i) (REG_ASRMCRA + (i << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_ASRFST(i) (REG_ASRFSTA + (i << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_ASRMCR1A 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_ASRMCR1B 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_ASRMCR1C 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_ASRMCR1(i) (REG_ASRMCR1A + (i << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* REG0 0x00 REG_ASRCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ASRCTR_ATSi_SHIFT(i) (20 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ASRCTR_ATSi_MASK(i) (1 << ASRCTR_ATSi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASRCTR_ATS(i) (1 << ASRCTR_ATSi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ASRCTR_USRi_SHIFT(i) (14 + (i << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ASRCTR_USRi_MASK(i) (1 << ASRCTR_USRi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ASRCTR_USR(i) (1 << ASRCTR_USRi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ASRCTR_IDRi_SHIFT(i) (13 + (i << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ASRCTR_IDRi_MASK(i) (1 << ASRCTR_IDRi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ASRCTR_IDR(i) (1 << ASRCTR_IDRi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ASRCTR_SRST_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ASRCTR_ASRCEi_SHIFT(i) (1 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ASRCTR_ASRCEi_MASK(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ASRCTR_ASRCE(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ASRCTR_ASRCEi_ALL_MASK (0x7 << ASRCTR_ASRCEi_SHIFT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ASRCTR_ASRCEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* REG1 0x04 REG_ASRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ASRIER_AFPWE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ASRIER_AOLIE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ASRIER_ADOEi_SHIFT(i) (3 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ASRIER_ADOEi_MASK(i) (1 << ASRIER_ADOEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ASRIER_ADOE(i) (1 << ASRIER_ADOEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ASRIER_ADIEi_SHIFT(i) (0 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ASRIER_ADIEi_MASK(i) (1 << ASRIER_ADIEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ASRIER_ADIE(i) (1 << ASRIER_ADIEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* REG2 0x0C REG_ASRCNCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ASRCNCR_ANCi_SHIFT(i, b) (b * i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ASRCNCR_ANCi_MASK(i, b) (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ASRCNCR_ANCi(i, v, b) ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* REG3 0x10 REG_ASRCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ASRCFG_INIRQi_SHIFT(i) (21 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ASRCFG_INIRQi_MASK(i) (1 << ASRCFG_INIRQi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ASRCFG_NDPRi_SHIFT(i) (18 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ASRCFG_NDPRi_ALL_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ASRCFG_POSTMODi_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ASRCFG_POSTMODi_DOWN(i) (2 << ASRCFG_POSTMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ASRCFG_PREMODi_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ASRCFG_PREMODi_DOWN(i) (2 << ASRCFG_PREMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ASRCFG_PREMODi_BYPASS(i) (3 << ASRCFG_PREMODi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* REG4 0x14 REG_ASRCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ASRCSR_AxCSi_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ASRCSR_AxCSi_MASK ((1 << ASRCSR_AxCSi_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ASRCSR_AOCSi_SHIFT(i) (12 + (i << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ASRCSR_AOCSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ASRCSR_AOCS(i, v) ((v) << ASRCSR_AOCSi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ASRCSR_AICSi_SHIFT(i) (i << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ASRCSR_AICSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ASRCSR_AICS(i, v) ((v) << ASRCSR_AICSi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ASRCDRi_AxCPi_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ASRCDRi_AICPi_SHIFT(i) (0 + (i % 2) * 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ASRCDRi_AICPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ASRCDRi_AICP(i, v) ((v) << ASRCDRi_AICPi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ASRCDRi_AICDi_SHIFT(i) (3 + (i % 2) * 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ASRCDRi_AICDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ASRCDRi_AICD(i, v) ((v) << ASRCDRi_AICDi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ASRCDRi_AOCPi_SHIFT(i) ((i < 2) ? 12 + i * 6 : 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ASRCDRi_AOCPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ASRCDRi_AOCP(i, v) ((v) << ASRCDRi_AOCPi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ASRCDRi_AOCDi_SHIFT(i) ((i < 2) ? 15 + i * 6 : 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ASRCDRi_AOCDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ASRCDRi_AOCD(i, v) ((v) << ASRCDRi_AOCDi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* REG7 0x20 REG_ASRSTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ASRSTR_DSLCNT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ASRSTR_ATQOL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ASRSTR_AOOLi_SHIFT(i) (17 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ASRSTR_AOOLi_MASK(i) (1 << ASRSTR_AOOLi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ASRSTR_AOOL(i) (1 << ASRSTR_AOOLi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ASRSTR_AIOLi_SHIFT(i) (14 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ASRSTR_AIOLi_MASK(i) (1 << ASRSTR_AIOLi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ASRSTR_AIOL(i) (1 << ASRSTR_AIOLi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ASRSTR_AODOi_SHIFT(i) (11 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ASRSTR_AODOi_MASK(i) (1 << ASRSTR_AODOi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ASRSTR_AODO(i) (1 << ASRSTR_AODOi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ASRSTR_AIDUi_SHIFT(i) (8 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ASRSTR_AIDUi_MASK(i) (1 << ASRSTR_AIDUi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ASRSTR_AIDU(i) (1 << ASRSTR_AIDUi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ASRSTR_FPWT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ASRSTR_AOLE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ASRSTR_AODEi_SHIFT(i) (3 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ASRSTR_AODFi_MASK(i) (1 << ASRSTR_AODEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ASRSTR_AODF(i) (1 << ASRSTR_AODEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ASRSTR_AIDEi_SHIFT(i) (0 + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ASRSTR_AIDEi_MASK(i) (1 << ASRSTR_AIDEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ASRSTR_AIDE(i) (1 << ASRSTR_AIDEi_SHIFT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* REG10 0x54 REG_ASRTFR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ASRTFR1_TF_BASE_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ASRTFR1_TF_BASE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ASRTFR1_TF_BASE(i) ((i) << ASRTFR1_TF_BASE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * REG22 0xA0 REG_ASRMCRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * REG24 0xA8 REG_ASRMCRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * REG26 0xB0 REG_ASRMCRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ASRMCRi_ZEROBUFi_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ASRMCRi_ZEROBUFi_MASK (1 << ASRMCRi_ZEROBUFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ASRMCRi_ZEROBUFi (1 << ASRMCRi_ZEROBUFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ASRMCRi_EXTTHRSHi_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ASRMCRi_EXTTHRSHi_MASK (1 << ASRMCRi_EXTTHRSHi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ASRMCRi_EXTTHRSHi (1 << ASRMCRi_EXTTHRSHi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ASRMCRi_BUFSTALLi_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ASRMCRi_BUFSTALLi_MASK (1 << ASRMCRi_BUFSTALLi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ASRMCRi_BUFSTALLi (1 << ASRMCRi_BUFSTALLi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ASRMCRi_BYPASSPOLYi_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ASRMCRi_BYPASSPOLYi_MASK (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ASRMCRi_BYPASSPOLYi (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ASRMCRi_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ASRMCRi_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ASRMCRi_RSYNIFi_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ASRMCRi_RSYNIFi_MASK (1 << ASRMCRi_RSYNIFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ASRMCRi_RSYNIFi (1 << ASRMCRi_RSYNIFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ASRMCRi_RSYNOFi_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ASRMCRi_RSYNOFi_MASK (1 << ASRMCRi_RSYNOFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ASRMCRi_RSYNOFi (1 << ASRMCRi_RSYNOFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ASRMCRi_INFIFO_THRESHOLD_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ASRMCRi_INFIFO_THRESHOLD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ASRMCRi_INFIFO_THRESHOLD_MASK (((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * REG23 0xA4 REG_ASRFSTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * REG25 0xAC REG_ASRFSTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * REG27 0xB4 REG_ASRFSTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ASRFSTi_OAFi_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ASRFSTi_OAFi_MASK (1 << ASRFSTi_OAFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ASRFSTi_OAFi (1 << ASRFSTi_OAFi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ASRFSTi_OUTPUT_FIFO_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ASRFSTi_OUTPUT_FIFO_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ASRFSTi_OUTPUT_FIFO_MASK (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ASRFSTi_IAEi_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ASRFSTi_IAEi_MASK (1 << ASRFSTi_IAEi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ASRFSTi_IAEi (1 << ASRFSTi_IAEi_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ASRFSTi_INPUT_FIFO_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ASRFSTi_INPUT_FIFO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ASRFSTi_INPUT_FIFO_MASK ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ASRMCR1i_IWD_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ASRMCR1i_IWD_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ASRMCR1i_IWD_MASK (((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ASRMCR1i_IWD(v) ((v) << ASRMCR1i_IWD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ASRMCR1i_IMSB_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ASRMCR1i_IMSB_MASK (1 << ASRMCR1i_IMSB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ASRMCR1i_IMSB_MSB (1 << ASRMCR1i_IMSB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ASRMCR1i_IMSB_LSB (0 << ASRMCR1i_IMSB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ASRMCR1i_OMSB_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ASRMCR1i_OMSB_MASK (1 << ASRMCR1i_OMSB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ASRMCR1i_OMSB_MSB (1 << ASRMCR1i_OMSB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ASRMCR1i_OMSB_LSB (0 << ASRMCR1i_OMSB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ASRMCR1i_OSGN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ASRMCR1i_OSGN_MASK (1 << ASRMCR1i_OSGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ASRMCR1i_OSGN (1 << ASRMCR1i_OSGN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ASRMCR1i_OW16_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ASRMCR1i_OW16_MASK (1 << ASRMCR1i_OW16_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum asrc_inclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) INCLK_NONE = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) INCLK_ESAI_RX = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) INCLK_SSI1_RX = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) INCLK_SSI2_RX = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) INCLK_SSI3_RX = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) INCLK_SPDIF_RX = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) INCLK_MLB_CLK = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) INCLK_PAD = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) INCLK_ESAI_TX = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) INCLK_SSI1_TX = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) INCLK_SSI2_TX = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) INCLK_SSI3_TX = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) INCLK_SPDIF_TX = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) INCLK_ASRCK1_CLK = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* clocks for imx8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) INCLK_AUD_PLL_DIV_CLK0 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) INCLK_AUD_PLL_DIV_CLK1 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) INCLK_AUD_CLK0 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) INCLK_AUD_CLK1 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) INCLK_ESAI0_RX_CLK = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) INCLK_ESAI0_TX_CLK = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) INCLK_SPDIF0_RX = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) INCLK_SPDIF1_RX = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) INCLK_SAI0_RX_BCLK = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) INCLK_SAI0_TX_BCLK = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) INCLK_SAI1_RX_BCLK = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) INCLK_SAI1_TX_BCLK = 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) INCLK_SAI2_RX_BCLK = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) INCLK_SAI3_RX_BCLK = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) INCLK_ASRC0_MUX_CLK = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) INCLK_ESAI1_RX_CLK = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) INCLK_ESAI1_TX_CLK = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) INCLK_SAI6_TX_BCLK = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) enum asrc_outclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) OUTCLK_NONE = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) OUTCLK_ESAI_TX = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) OUTCLK_SSI1_TX = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) OUTCLK_SSI2_TX = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) OUTCLK_SSI3_TX = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) OUTCLK_SPDIF_TX = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) OUTCLK_MLB_CLK = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) OUTCLK_PAD = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) OUTCLK_ESAI_RX = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) OUTCLK_SSI1_RX = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) OUTCLK_SSI2_RX = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) OUTCLK_SSI3_RX = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) OUTCLK_SPDIF_RX = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) OUTCLK_ASRCK1_CLK = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* clocks for imx8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) OUTCLK_AUD_PLL_DIV_CLK0 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) OUTCLK_AUD_PLL_DIV_CLK1 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) OUTCLK_AUD_CLK0 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) OUTCLK_AUD_CLK1 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) OUTCLK_ESAI0_RX_CLK = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) OUTCLK_ESAI0_TX_CLK = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) OUTCLK_SPDIF0_RX = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) OUTCLK_SPDIF1_RX = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) OUTCLK_SAI0_RX_BCLK = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) OUTCLK_SAI0_TX_BCLK = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) OUTCLK_SAI1_RX_BCLK = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) OUTCLK_SAI1_TX_BCLK = 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) OUTCLK_SAI2_RX_BCLK = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) OUTCLK_SAI3_RX_BCLK = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) OUTCLK_ASRCO_MUX_CLK = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) OUTCLK_ESAI1_RX_CLK = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) OUTCLK_ESAI1_TX_CLK = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) OUTCLK_SAI6_TX_BCLK = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define ASRC_CLK_MAX_NUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ASRC_CLK_MAP_LEN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) enum asrc_word_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ASRC_WIDTH_24_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ASRC_WIDTH_16_BIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ASRC_WIDTH_8_BIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct asrc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) enum asrc_pair_index pair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned int channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int buffer_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int dma_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int input_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int output_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) snd_pcm_format_t input_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) snd_pcm_format_t output_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) enum asrc_inclk inclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) enum asrc_outclk outclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct asrc_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int chn_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enum asrc_pair_index index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct asrc_querybuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int buffer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int input_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int output_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long input_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct asrc_convert_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void *input_buffer_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void *output_buffer_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int input_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int output_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct asrc_status_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enum asrc_pair_index index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int overload_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) enum asrc_error_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ASRC_TASK_Q_OVERLOAD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ASRC_INPUT_TASK_OVERLOAD = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct dma_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dma_addr_t dma_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void *dma_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * fsl_asrc_soc_data: soc specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @use_edma: using edma as dma device or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @channel_bits: width of ASRCNCR register for each pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct fsl_asrc_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bool use_edma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int channel_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * fsl_asrc_pair_priv: ASRC Pair private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @config: configuration profile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct fsl_asrc_pair_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct asrc_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * fsl_asrc_priv: ASRC private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @asrck_clk: clock sources to driver ASRC internal logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * @soc: soc specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * @clk_map: clock map for input/output clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @regcache_cfg: store register value of REG_ASRCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct fsl_asrc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const struct fsl_asrc_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned char *clk_map[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 regcache_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif /* _FSL_ASRC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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