^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __DESIGNWARE_LOCAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DESIGNWARE_LOCAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/designware_i2s.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* common register for all channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IER 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IRER 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ITER 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CER 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCR 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RXFFR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TXFFR 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Interrupt status register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISR_TXFO BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ISR_TXFE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISR_RXFO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ISR_RXDA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* I2STxRxRegisters for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LRBR_LTHR(x) (0x40 * x + 0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RRBR_RTHR(x) (0x40 * x + 0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RER(x) (0x40 * x + 0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TER(x) (0x40 * x + 0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RCR(x) (0x40 * x + 0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TCR(x) (0x40 * x + 0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ISR(x) (0x40 * x + 0x038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMR(x) (0x40 * x + 0x03C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ROR(x) (0x40 * x + 0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TOR(x) (0x40 * x + 0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RFCR(x) (0x40 * x + 0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TFCR(x) (0x40 * x + 0x04C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RFF(x) (0x40 * x + 0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TFF(x) (0x40 * x + 0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* I2SCOMPRegisters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2S_COMP_PARAM_2 0x01F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2S_COMP_PARAM_1 0x01F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2S_COMP_VERSION 0x01F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2S_COMP_TYPE 0x01FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Component parameter register fields - define the I2S block's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define COMP_MAX_WORDSIZE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define COMP_MAX_DATA_WIDTH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX_CHANNEL_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MIN_CHANNEL_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) union dw_i2s_snd_dma_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2s_dma_data pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct snd_dmaengine_dai_dma_data dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct dw_i2s_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *i2s_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int i2s_reg_comp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int i2s_reg_comp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 xfer_resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 fifo_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* data related to DMA transfers b/w i2s and DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) union dw_i2s_snd_dma_data play_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) union dw_i2s_snd_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct i2s_clk_config_data config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* data related to PIO transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool use_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct snd_pcm_substream __rcu *tx_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct snd_pcm_substream __rcu *rx_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int (*tx_fn)(struct dw_i2s_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool *period_elapsed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int (*rx_fn)(struct dw_i2s_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool *period_elapsed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int tx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int rx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void dw_pcm_push_tx(struct dw_i2s_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void dw_pcm_pop_rx(struct dw_i2s_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int dw_pcm_register(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void dw_pcm_push_tx(struct dw_i2s_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int dw_pcm_register(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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