Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * ALSA SoC Synopsys PIO PCM for I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * sound/soc/dwc/designware_pcm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2016 Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Jose Abreu <joabreu@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/rcupdate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define BUFFER_BYTES_MAX	(3 * 2 * 8 * PERIOD_BYTES_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PERIOD_BYTES_MIN	4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PERIODS_MIN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define dw_pcm_tx_fn(sample_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static unsigned int dw_pcm_tx_##sample_bits(struct dw_i2s_dev *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		struct snd_pcm_runtime *runtime, unsigned int tx_ptr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		bool *period_elapsed) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	const u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned int period_pos = tx_ptr % runtime->period_size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	for (i = 0; i < dev->fifo_th; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		iowrite32(p[tx_ptr][0], dev->i2s_base + LRBR_LTHR(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		iowrite32(p[tx_ptr][1], dev->i2s_base + RRBR_RTHR(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		period_pos++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		if (++tx_ptr >= runtime->buffer_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			tx_ptr = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	*period_elapsed = period_pos >= runtime->period_size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return tx_ptr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define dw_pcm_rx_fn(sample_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static unsigned int dw_pcm_rx_##sample_bits(struct dw_i2s_dev *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		struct snd_pcm_runtime *runtime, unsigned int rx_ptr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		bool *period_elapsed) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int period_pos = rx_ptr % runtime->period_size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	for (i = 0; i < dev->fifo_th; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		p[rx_ptr][0] = ioread32(dev->i2s_base + LRBR_LTHR(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		p[rx_ptr][1] = ioread32(dev->i2s_base + RRBR_RTHR(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		period_pos++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		if (++rx_ptr >= runtime->buffer_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			rx_ptr = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	*period_elapsed = period_pos >= runtime->period_size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return rx_ptr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) dw_pcm_tx_fn(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) dw_pcm_tx_fn(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) dw_pcm_rx_fn(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) dw_pcm_rx_fn(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #undef dw_pcm_tx_fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #undef dw_pcm_rx_fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct snd_pcm_hardware dw_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		SNDRV_PCM_INFO_BLOCK_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.rates = SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.buffer_bytes_max = BUFFER_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.period_bytes_min = PERIOD_BYTES_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.periods_min = PERIODS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void dw_pcm_transfer(struct dw_i2s_dev *dev, bool push)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bool active, period_elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (push)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		substream = rcu_dereference(dev->tx_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		substream = rcu_dereference(dev->rx_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	active = substream && snd_pcm_running(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		unsigned int ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		unsigned int new_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		if (push) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			ptr = READ_ONCE(dev->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					&period_elapsed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			cmpxchg(&dev->tx_ptr, ptr, new_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			ptr = READ_ONCE(dev->rx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 					&period_elapsed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			cmpxchg(&dev->rx_ptr, ptr, new_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (period_elapsed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void dw_pcm_push_tx(struct dw_i2s_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	dw_pcm_transfer(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void dw_pcm_pop_rx(struct dw_i2s_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dw_pcm_transfer(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int dw_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		       struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	snd_soc_set_runtime_hwparams(substream, &dw_pcm_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	runtime->private_data = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int dw_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	synchronize_rcu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int dw_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			    struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			    struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct dw_i2s_dev *dev = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	switch (params_channels(hw_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(dev->dev, "invalid channels number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	switch (params_format(hw_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		dev->tx_fn = dw_pcm_tx_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev->rx_fn = dw_pcm_rx_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev->tx_fn = dw_pcm_tx_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev->rx_fn = dw_pcm_rx_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(dev->dev, "invalid format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int dw_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			  struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct dw_i2s_dev *dev = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			WRITE_ONCE(dev->tx_ptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			rcu_assign_pointer(dev->tx_substream, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			WRITE_ONCE(dev->rx_ptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			rcu_assign_pointer(dev->rx_substream, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			rcu_assign_pointer(dev->tx_substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			rcu_assign_pointer(dev->rx_substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static snd_pcm_uframes_t dw_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct dw_i2s_dev *dev = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	snd_pcm_uframes_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		pos = READ_ONCE(dev->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		pos = READ_ONCE(dev->rx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return pos < runtime->buffer_size ? pos : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int dw_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		      struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	size_t size = dw_pcm_hardware.buffer_bytes_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	snd_pcm_set_managed_buffer_all(rtd->pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			SNDRV_DMA_TYPE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			NULL, size, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct snd_soc_component_driver dw_pcm_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.open		= dw_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.close		= dw_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.hw_params	= dw_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.trigger	= dw_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.pointer	= dw_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.pcm_construct	= dw_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int dw_pcm_register(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return devm_snd_soc_register_component(&pdev->dev, &dw_pcm_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 					       NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }