^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ASoC driver for Cirrus Logic EP93xx AC97 controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010 Mika Westerberg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_data/dma-ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/soc/cirrus/ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ep93xx-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Per channel (1-4) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AC97CH(n) (((n) - 1) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AC97DR(n) (AC97CH(n) + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AC97RXCR(n) (AC97CH(n) + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AC97RXCR_REN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AC97RXCR_RX3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AC97RXCR_RX4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AC97RXCR_CM BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AC97TXCR(n) (AC97CH(n) + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AC97TXCR_TEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AC97TXCR_TX3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AC97TXCR_TX4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AC97TXCR_CM BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AC97SR(n) (AC97CH(n) + 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AC97SR_TXFE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AC97SR_TXUE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AC97RISR(n) (AC97CH(n) + 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AC97ISR(n) (AC97CH(n) + 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AC97IE(n) (AC97CH(n) + 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Global AC97 controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AC97S1DATA 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AC97S2DATA 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AC97S12DATA 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AC97RGIS 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AC97GIS 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AC97IM 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Common bits for RGIS, GIS and IM registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AC97_SLOT2RXVALID BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AC97_CODECREADY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AC97_SLOT2TXCOMPLETE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AC97EOI 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AC97EOI_WINT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AC97EOI_CODECREADY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AC97GCR 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AC97GCR_AC97IFE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AC97RESET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AC97RESET_TIMEDRESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AC97SYNC 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AC97SYNC_TIMEDSYNC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AC97_TIMEOUT msecs_to_jiffies(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @dev: pointer to the platform device dev structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @regs: mapped AC97 controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @done: bus ops wait here for an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ep93xx_ac97_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct snd_dmaengine_dai_dma_data dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* currently ALSA only supports a single AC97 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct ep93xx_ac97_info *ep93xx_ac97_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "ac97-pcm-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .port = EP93XX_DMA_AAC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .direction = DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "ac97-pcm-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .port = EP93XX_DMA_AAC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .direction = DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return __raw_readl(info->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned reg, unsigned val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __raw_writel(val, info->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ep93xx_ac97_info *info = ep93xx_ac97_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_warn(info->dev, "timeout reading register %x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void ep93xx_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct ep93xx_ac97_info *info = ep93xx_ac97_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Writes to the codec need to be done so that slot 2 is filled in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * before slot 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ep93xx_ac97_write_reg(info, AC97S2DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_warn(info->dev, "timeout writing register %x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct ep93xx_ac97_info *info = ep93xx_ac97_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * We are assuming that before this functions gets called, the codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * control the SYNC signal directly via AC97SYNC register. Using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * TIMEDSYNC the controller will keep the SYNC high > 1us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_warn(info->dev, "codec warm reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ep93xx_ac97_info *info = ep93xx_ac97_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * For doing cold reset, we disable the AC97 controller interface, clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * WINT and CODECREADY bits, and finally enable the interface again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ep93xx_ac97_write_reg(info, AC97GCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Now, assert the reset and wait for the codec to become ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_warn(info->dev, "codec cold reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Give the codec some time to come fully out from the reset. This way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * we ensure that the subsequent reads/writes will work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) usleep_range(15000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct ep93xx_ac97_info *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned status, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Just mask out the interrupt and wake up the waiting thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * the waiting thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) status = ep93xx_ac97_read_reg(info, AC97GIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mask = ep93xx_ac97_read_reg(info, AC97IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mask &= ~status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ep93xx_ac97_write_reg(info, AC97IM, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) complete(&info->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct snd_ac97_bus_ops ep93xx_ac97_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .read = ep93xx_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .write = ep93xx_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .reset = ep93xx_ac97_cold_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .warm_reset = ep93xx_ac97_warm_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Enable compact mode, TX slots 3 & 4, and the TX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) v |= AC97TXCR_CM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) v |= AC97TXCR_TX3 | AC97TXCR_TX4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) v |= AC97TXCR_TEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Enable compact mode, RX slots 3 & 4, and the RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) v |= AC97RXCR_CM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) v |= AC97RXCR_RX3 | AC97RXCR_RX4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) v |= AC97RXCR_REN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * As per Cirrus EP93xx errata described below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * https://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * we will wait for the TX FIFO to be empty before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * clearing the TEN bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned long timeout = jiffies + AC97_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) v = ep93xx_ac97_read_reg(info, AC97SR(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_warn(info->dev, "TX timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* disable the TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* disable the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_warn(info->dev, "unknown command %d\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dai->playback_dma_data = &info->dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dai->capture_dma_data = &info->dma_params_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .trigger = ep93xx_ac97_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct snd_soc_dai_driver ep93xx_ac97_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "ep93xx-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .probe = ep93xx_ac97_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .stream_name = "AC97 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .stream_name = "AC97 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ops = &ep93xx_ac97_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct snd_soc_component_driver ep93xx_ac97_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "ep93xx-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ep93xx_ac97_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct ep93xx_ac97_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) info->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(info->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(info->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return irq < 0 ? irq : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) IRQF_TRIGGER_HIGH, pdev->name, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_set_drvdata(&pdev->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mutex_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) init_completion(&info->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ep93xx_ac97_info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) &ep93xx_ac97_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = devm_ep93xx_pcm_platform_register(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto fail_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) fail_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ep93xx_ac97_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int ep93xx_ac97_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* disable the AC97 controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ep93xx_ac97_write_reg(info, AC97GCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ep93xx_ac97_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct platform_driver ep93xx_ac97_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .probe = ep93xx_ac97_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .remove = ep93xx_ac97_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = "ep93xx-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) module_platform_driver(ep93xx_ac97_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_ALIAS("platform:ep93xx-ac97");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags